Double poly trenched channel accelerated tunneling electron (DPT-CATE) cell, for memory applications

Claim 1

A non-volatile memory cell capable of being electrically erased by tunneling and programmed using the electrons in the channel directly, by channel accelerated carrier tunneling, comprising, a semiconducting substrate, doped with an impurity of a first type a buried layer, doped with an impurity of a second type opposite the impurity of the first type, introduced into the substrate, an epitaxial layer having an impurity of the first type deposed on the substrate, a trench in the epitaxial layer producing a step at a surface, a gate oxide deposed on a side wall of the trench, a source formed by an implant of the impurity of the first type into the bottom of the trench, the source doping making contact to the buried layer doping, a tunnel oxide deposed on the surface of the epitaxial layer adjacent the trench, a first conductive layer deposed over the gate oxide and the tunnel oxide forming a floating gate storage node, an interlayer dielectric deposed over the first conductive layer, a second conductive layer deposed over the first conductive layer, separated from it by, but capacitively coupled to it through, the interlayer dielectric, a drain formed on the surface of the epitaxial layer, spaced away from the side wall of the trench, by doping the epitaxial layer with an impurity of the second type, the drain driven under the tunnel oxide and floating gate providing an area for tunnel erase from the floating gate to the dram through the tunnel oxide, a channel under the gate oxide and tunnel oxide, between the source and the drain, a discontinuity in the channel at the intersection of the sidewall with the gate oxide and the surface of the epitaxial layer with the tunnel oxide thereon, enabling write by channel accelerated career tunneling, a third conductive layer making contact to the dram at a contact forming a bit line.