Method of making flash EEPROM memory cell

Claim 1

The method of forming a memory cell with reduced coupling ratio and improved short channel effect comprising: providing field oxide regions in and on a semiconductor substrate; forming lightly doped drain regions within said semiconductor substrate; covering said substrate with a photoresist layer and patterning said photoresist layer; etching a trench into said substrate using said patterned photoresist layer as a mask wherein said trench will provide an increased channel length reducing said short-channel effect; removing said photoresist layer; forming a gate oxide layer over the surface of said substrate and within said trench; depositing a layer of silicon nitride over said gate oxide layer; anisotropically etching said silicon nitride layer to leave spacers on the sidewalls of said trench; overetching said spacers to expose an upper portion of said gate oxide layer on said sidewalls of said trench; removing said gate oxide layer not covered by said spacers wherein the horizontal silicon surface of said substrate at the bottom of said trench and the upper portion of the silicon sidewalls of said trench above said spacers are exposed; growing a tunnel oxide layer on the exposed silicon surfaces of said substrate and within said trench wherein the tunnel oxide within said trench provides an improved coupling ratio of said memory cell; removing said silicon nitride spacers; depositing a first polysilicon layer over the surface of said tunnel oxide and said gate oxide layers within said trench and doping said first polysilicon layer; depositing an interpoly dielectric layer over said first polysilicon layer; depositing a second polysilicon layer overlying said dielectric layer and doping said second polysilicon layer; patterning said first and second polysilicon layers and said dielectric layer to form a stacked polysilicon structure wherein said first polysilicon layer forms a floating gate and said second polysilicon layer forms a control gate; implanting ions into said substrate using said stacked polysilicon structure as a mask to form heavily doped source and drain regions on opposite sides of said stacked polysilicon structure; forming silicon oxide spacers on the sidewalls of said stacked polysilicon structure; and providing passivation and metallization to complete the fabrication of said memory cell with improved coupling ratio and reduced short channel effect.

Claim 2

The method of forming a memory cell with reduced coupling ratio and improved short channel effect comprising: providing field oxide regions in and on a semiconductor substrate; forming lightly doped drain regions within said semiconductor substrate; covering said substrate with a photoresist layer and patterning said photoresist layer; etching a trench into said substrate using said patterned photoresist layer as a mask wherein said trench will provide an increased channel length reducing said short-channel effect; removing said photoresist layer; forming a gate oxide layer over the surface of said substrate and within said trench; depositing a layer of silicon nitride over said gate oxide layer; anisotropically etching said silicon nitride layer to leave spacers on the sidewalls of said trench; overetching said spacers to expose an upper portion of said gate oxide layer on said sidewalls of said trench; removing said gate oxide layer not covered by said spacers wherein the horizontal silicon surface of said substrate at the bottom of said trench and the upper portion of the silicon sidewalls of said trench above said spacers are exposed; growing a tunnel oxide layer on the exposed silicon surfaces of said substrate and within said trench wherein the tunnel oxide within said trench provides an improved coupling ratio of said memory cell; removing said silicon nitride spacers; depositing a first polysilicon layer over the surface of said tunnel oxide and said gate oxide layers within said trench and doping said first polysilicon layer; depositing an interpoly dielectric layer over said first polysilicon layer; depositing a second polysilicon layer overlying said dielectric layer and doping said second polysilicon layer; patterning said first and second polysilicon layers and said dielectric layer to form a stacked polysilicon structure wherein said first polysilicon layer forms a floating gate and said second polysilicon layer forms a control gate; implanting ions into said substrate using said stacked polysilicon structure as a mask to form heavily doped source and drain regions on opposite sides of said stacked polysilicon structure; forming silicon oxide spacers on the sidewalls of said stacked polysilicon structure; and providing passivation and metallization to complete the fabrication of said memory cell with improved coupling ratio and reduced short channel effect.

Claim 15

The method of forming a memory cell with improved coupling ratio and reduced short channel effect comprising: providing field oxide regions in and on a semiconductor substrate; covering said substrate with a photoresist layer and patterning said photoresist layer; etching a trench into said substrate using said patterned photoresist layer as a mask wherein said trench will provide an increased channel length reducing said short channel effect; removing said photoresist layer; forming a gate oxide layer over the surface of said substrate and within said trench; depositing a layer of silicon nitride over said gate oxide layer; anisotropically etching said silicon nitride layer to leave spacers on the sidewalls of said trench; overetching said spacers to expose an upper portion of said gate oxide layer on said sidewalls of said trench; removing said gate oxide layer not covered by said spacers wherein the horizontal silicon surface of said substrate at the bottom of said trench and the upper portion of the silicon sidewalls of said trench above said spacers are exposed; growing a tunnel oxide layer on the exposed silicon surfaces of said substrate and within said trench wherein the tunnel oxide within said trench provides an improved coupling ratio of said memory cell; removing said silicon nitride spacers; depositing a first polysilicon layer over the surface of said tunnel oxide and said gate oxide layers within said trench and doping said first polysilicon layer; planarizing said first polysilicon layer so that said first polysilicon layer remains only within said trench and wherein said first polysilicon layer forms a floating gate; implanting ions into said substrate to form source and drain regions on opposite sides of said floating gate; depositing an interpoly dielectric layer over the surface of said substrate and over said floating gate; depositing a second polysilicon layer overlying said interpoly dielectric layer and doping said second polysilicon layer; patterning said second polysilicon layer to form a control gate; and providing passivation and metallization to complete the fabrication of said memory cell with improved coupling ratio and reduced short channel effect.

Claim 16

The method of forming a memory cell with improved coupling ratio and reduced short channel effect comprising: providing field oxide regions in and on a semiconductor substrate; covering said substrate with a photoresist layer and patterning said photoresist layer; etching a trench into said substrate using said patterned photoresist layer as a mask wherein said trench will provide an increased channel length reducing said short channel effect; removing said photoresist layer; forming a gate oxide layer over the surface of said substrate and within said trench; depositing a layer of silicon nitride over said gate oxide layer; anisotropically etching said silicon nitride layer to leave spacers on the sidewalls of said trench; overetching said spacers to expose an upper portion of said gate oxide layer on said sidewalls of said trench; removing said gate oxide layer not covered by said spacers wherein the horizontal silicon surface of said substrate at the bottom of said trench and the upper portion of the silicon sidewalls of said trench above said spacers are exposed; growing a tunnel oxide layer on the exposed silicon surfaces of said substrate and within said trench wherein the tunnel oxide within said trench provides an improved coupling ratio of said memory cell; removing said silicon nitride spacers; depositing a first polysilicon layer over the surface of said tunnel oxide and said gate oxide layers within said trench and doping said first polysilicon layer; planarizing said first polysilicon layer so that said first polysilicon layer remains only within said trench and wherein said first polysilicon layer forms a floating gate; implanting ions into said substrate to form source and drain regions on opposite sides of said floating gate; depositing an interpoly dielectric layer over the surface of said substrate and over said floating gate; depositing a second polysilicon layer overlying said interpoly dielectric layer and doping said second polysilicon layer; patterning said second polysilicon layer to form a control gate; and providing passivation and metallization to complete the fabrication of said memory cell with improved coupling ratio and reduced short channel effect.