Patent US5974041A successfully refreshed from Google Patents.
US5974041A
Expired / Lapsed
US
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Efficient parallel-stage power amplifier
Assignee: Qualcomm Inc
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Filing: 1995-12-27
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Granted: 1999-10-26
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Expires: 2015-12-27
Abstract
Abstract An amplifier circuit for providing an amplified signal in response to an input signal. The amplifier circuit includes an input network for applying the input signal to a selected at least one of a plurality of amplifier stages. An output network is provided for coupling the amplified signal from the selected at least one amplifier stage. The appropriate amplifier stage is selected by a control circuit in response to a desired power value of the amplified signal. By selectively activating only the amplifier stage(s) that are necessary to provide the desired level of output power, increased DC efficiency can be accomplished in applications that require an amplifier which operates linearly over a wide dynamic range.
Inventors
- 👤 Richard K. Kornfeld
- 👤 Charles E. Wheatley, III
- 👤 Richard J. Camarillo
- 👤 Katherine W. White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:41
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/20; H03F3/21; H03F3/211; H03F1/00; H03F1/02; H03F1/0205; H03F1/0277; H03F1/0288; H03F3/24; H03F3/602; H03F3/72; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/3036; H03G3/3042; H04; H04B; H04B1/00; H04B1/02; H04B1/04; H04B1/0483; H03F2200/00; H03F2200/294; H03F2203/00; H03F2203/72; H03F2203/7236; H04B2001/0408
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
227 words
An amplifier circuit for providing an amplified signal in response to an input signal, said amplifier circuit comprising: a plurality of amplifier stages coupled in parallel for amplifying said input signal, each of said plurality of amplifier stages having an amplifier stage input coupled to said input signal and an amplifier stage output for providing said amplified signal; a control circuit, coupled to each of said plurality of amplifier stages, for selecting at least one of said plurality of amplifier stages in response to a power level of said amplified signal; an input network having an input coupled to said input signal and a plurality of outputs, each output coupled to one of said amplifier stage inputs, said input network for providing said input signal to a selected at least one of said plurality of amplifier stages; an output network coupled to each of said amplifier stage outputs, for providing said amplified signal from said selected at least one of said plurality of amplifier stages at an output network output node; and a plurality of power matching networks, each of said plurality of power matching networks having a power matching input coupled to a respective one of said amplifier stage outputs and having a power matching output coupled to an output node, said plurality of power matching networks for providing said amplified signal at said output node.
Claim 2
Dependent Claim
227 words
An amplifier circuit for providing an amplified signal in response to an input signal, said amplifier circuit comprising: a plurality of amplifier stages coupled in parallel for amplifying said input signal, each of said plurality of amplifier stages having an amplifier stage input coupled to said input signal and an amplifier stage output for providing said amplified signal; a control circuit, coupled to each of said plurality of amplifier stages, for selecting at least one of said plurality of amplifier stages in response to a power level of said amplified signal; an input network having an input coupled to said input signal and a plurality of outputs, each output coupled to one of said amplifier stage inputs, said input network for providing said input signal to a selected at least one of said plurality of amplifier stages; an output network coupled to each of said amplifier stage outputs, for providing said amplified signal from said selected at least one of said plurality of amplifier stages at an output network output node; and a plurality of power matching networks, each of said plurality of power matching networks having a power matching input coupled to a respective one of said amplifier stage outputs and having a power matching output coupled to an output node, said plurality of power matching networks for providing said amplified signal at said output node.
Claim 3
Dependent Claim
45 words
The amplifier circuit of claim 1 wherein said input network comprises an input switch, coupled to said control circuit and controlled by said control circuit and wherein said output network comprises an output switch, coupled to said control circuit and controlled by said control circuit.
Claim 4
Dependent Claim
172 words
The amplifier circuit of claim 1 wherein said control circuit generates a gain adjust signal in response to said measured power level of said amplified signal and wherein said input network comprises: an input divider circuit for dividing said input signal into a plurality of input signal components of a predetermined phase; and a plurality of gain adjust elements, each of said plurality of gain adjust elements having a gain adjust input coupled to said input divider circuit for receiving a respective one of said plurality of input signal components, and each of said plurality of gain adjust elements having a gain adjust output coupled to a respective one of said amplifier stage inputs, each of said plurality of gain adjust elements for adjusting a respective power level of said respective one of said plurality of input signal components in response to said gain adjust signal; and said output network comprises an output combiner circuit for combining said plurality of input signal components of a predetermined phase into a combined amplified signal.
Claim 5
Dependent Claim
96 words
The amplifier circuit of claim 1 wherein further comprising: a plurality of transistors, each of said plurality of transistors having a transistor input coupled to a respective one of said amplifier stage outputs and having a transistor output, each of said plurality of transistors being selectively activated by said respective one of said amplifier stages; and a power matching network having a power matching input coupled to each of said transistor outputs, and having a power matching output coupled to an output node, said power matching network for providing said amplified signal at said output node.
Claim 6
Dependent Claim
49 words
The amplifier circuit of claim 1 wherein said plurality of amplifier stages comprises: a low power amplifier for receiving said input signal and generating a low power amplifier signal; and a high power amplifier coupled to said low power amplifier for receiving and amplifying said low power amplifier signal.
Claim 7
Dependent Claim
248 words
In a cellular communication system in which a plurality of users use radiotelephones to communicate information signals between one another via at least one cell site using code division multiple access (CDMA) spread spectrum communication signals, a radiotelephone transmit amplifier circuit disposed within said radiotelephone for providing an amplified CDMA signal in response to an input CDMA signal, said transmit amplifier circuit comprising: a plurality of amplifier stages coupled in parallel for amplifying said input CDMA signal, each of said plurality of amplifier stages having an amplifier stage input and an amplifier stage output; an input network, coupled to each of said amplifier stage inputs of said plurality of amplifier stages, for providing said input CDMA signal to a selected at least one of said plurality of amplifier stages; an output network, coupled to each of said amplifier stage outputs of said plurality of amplifier stages, for providing said amplified CDMA signal at an output network output node; a control circuit, coupled to said input network and said output network, for selecting said at least one of said plurality of amplifier stages in response to a power level of said amplified CDMA signal; and an amplifier circuit wherein said input signal comprises a sequence of code symbols, said control circuit for identifying transitions between said code symbols and enabling said input network to provide said input signal to a different selected at least one of said plurality of amplifier stages only at said transitions between said code symbols.
Claim 8
Dependent Claim
248 words
In a cellular communication system in which a plurality of users use radiotelephones to communicate information signals between one another via at least one cell site using code division multiple access (CDMA) spread spectrum communication signals, a radiotelephone transmit amplifier circuit disposed within said radiotelephone for providing an amplified CDMA signal in response to an input CDMA signal, said transmit amplifier circuit comprising: a plurality of amplifier stages coupled in parallel for amplifying said input CDMA signal, each of said plurality of amplifier stages having an amplifier stage input and an amplifier stage output; an input network, coupled to each of said amplifier stage inputs of said plurality of amplifier stages, for providing said input CDMA signal to a selected at least one of said plurality of amplifier stages; an output network, coupled to each of said amplifier stage outputs of said plurality of amplifier stages, for providing said amplified CDMA signal at an output network output node; a control circuit, coupled to said input network and said output network, for selecting said at least one of said plurality of amplifier stages in response to a power level of said amplified CDMA signal; and an amplifier circuit wherein said input signal comprises a sequence of code symbols, said control circuit for identifying transitions between said code symbols and enabling said input network to provide said input signal to a different selected at least one of said plurality of amplifier stages only at said transitions between said code symbols.
Claim 9
Dependent Claim
25 words
The amplifier circuit of claim 6 wherein said control circuit comprises a gain control loop for controlling a gain setting of said high power amplifier.
References Cited (Backward Citations)
US3325738A
Cited
US3469195A
Cited
US3514710A
Cited
US3665507A
Cited
US3886380A
Cited
US4263560A
Cited
US4054849A
Cited
US4041396A
Cited
US4223274A
Cited
US4158180A
Cited
US4207538A
Cited
US4320350A
Cited
US4380711A
Cited
US4500848A
Cited
US4426625A
Cited
US4439744A
Cited
US4514702A
Cited
US4578603A
Cited
US4447783A
Cited
US4560949A
Cited
US4510460A
Cited
JPS5997213A
Cited
US4495648A
Cited
US4523155A
Cited
US4607234A
Cited
US4593409A
Cited
US4654882A
Cited
US4613990A
Cited
US4592252A
Cited
US4661993A
Cited
US4709403A
Cited
US4602218A
Cited
US4723304A
Cited
US4740964A
Cited
US4901307A
Cited
US4870698A
Cited
US4797632A
Cited
US4727337A
Cited
US4816772A
Cited
US5163181A
Cited
US4901032A
Cited
US5029298A
Cited
US4893093A
Cited
US5152004A
Cited
US5083096A
Cited
US5251330A
Cited
US5146180A
Cited
US5256987A
Cited
US5099204A
Cited
US5107225A
Cited
US5132634A
Cited
US5136300A
Cited
US5175871A
Cited
US5192919A
Cited
US5287543A
Cited
EP0537733A2
Cited
US5487185A
Cited
US5438684A
Cited
US5329548A
Cited
EP0594358A2
Cited
US5339046A
Cited
US5542096A
Cited
US5541554A
Cited
US5608353A
Cited
US5568086A
Cited
US5678208A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-25 | 2003-04-26 | 2003-10-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-25 | 2007-04-26 | 2007-10-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-25 | 2011-04-26 | 2011-10-26 | $7700.00 | Window Closed / Lapsed |