Patent US5966724A successfully refreshed from Google Patents.
US5966724A
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Synchronous memory device with dual page and burst mode operations
Assignee: Micron Technology Inc
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Filing: 1996-01-11
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Granted: 1999-10-12
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Expires: 2016-01-11
Abstract
Abstract A synchronous burst access memory device fits in a standard Fast Page Mode DRAM package. The device is adapted to receive a free running system clock, a Byte Enable input (BE) and a Burst Control input (BC). The burst access memory device has an internal column address counter for burst accesses, but is capable of receiving a new column address with each clock edge in a page access to provide for random access of the memory. A data pipeline allows for high clock speeds and high data throughput. The state of the byte enable pin when the row address is latched determines whether a refresh cycle or a data access is to be performed. The BC input is also used to mask the clock input during row address strobe to column address strobe delay periods (tRCD). The clock input is used as a column address strobe after tRCD. A write enable input selects between read and write access cycles. The BC input determines whether the column address for the current cycle will be a new address latched from a source external to the memory device, or an internally generated address from the address counter.
Inventors
- 👤 Kevin J. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:48
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1024; G11C7/1027
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
205 words
A Synchronous memory device adapted to receive a free running clock input signal, comprising: a plurality of addressable memory data storage cells arranged in rows and columns; a row address strobe (RAS) input adapted to receive a RAS signal which enables a row address latch to receive a row address in response to the clock signal; a byte enable (BE) input adapted to receive a BE signal which enables the burst access memory to output data in a read cycle and to store data in a write cycle, the BE signal also selecting between an access cycle and a refresh cycle; a column address circuit; and a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling said column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling said column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.
Claim 2
Dependent Claim
205 words
A Synchronous memory device adapted to receive a free running clock input signal, comprising: a plurality of addressable memory data storage cells arranged in rows and columns; a row address strobe (RAS) input adapted to receive a RAS signal which enables a row address latch to receive a row address in response to the clock signal; a byte enable (BE) input adapted to receive a BE signal which enables the burst access memory to output data in a read cycle and to store data in a write cycle, the BE signal also selecting between an access cycle and a refresh cycle; a column address circuit; and a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling said column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling said column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.
Claim 3
Dependent Claim
31 words
The burst access memory device of claim 1, wherein the BE signal selects between an access cycle and a refresh cycle within one clock period of receipt of the row address.
Claim 4
Dependent Claim
40 words
The burst access memory device of claim 1, further having inputs consisting essentially of: at least one supply input; at least one ground input; a write enable input; a plurality of address inputs; and a plurality of data input/output nodes.
Claim 5
Dependent Claim
160 words
A Synchronous memory device comprising: a plurality of addressable memory data storage cells arranged in rows and columns; a supply input; a ground input; an address input; a dat input/output; and a plurality of control signal inputs consisting essentially of: a write enable input; a byte enable input; a row address strobe input; a clock input for a clock signal; and a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling a column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling the column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.
Claim 6
Dependent Claim
160 words
A Synchronous memory device comprising: a plurality of addressable memory data storage cells arranged in rows and columns; a supply input; a ground input; an address input; a dat input/output; and a plurality of control signal inputs consisting essentially of: a write enable input; a byte enable input; a row address strobe input; a clock input for a clock signal; and a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling a column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling the column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.
Claim 7
Dependent Claim
33 words
The memory device of claim 4, wherein a byte enable signal received by said byte enable input is operative to select between a refresh cycle and an access cycle of the memory device.
Claim 8
Dependent Claim
25 words
The memory device of claim 5, wherein the byte enable signal is further adapted to enable data input and data output of the memory device.
Claim 9
Independent Claim
214 words
An apparatus comprising: a burst access memory device adapted to receive a free running clock input signal, said burst access memory device comprising: a plurality of addressable memory data storage cells arranged in rows and columns; a row address strobe (RAS) input adapted to receive a RAS signal which enables a row address latch to receive a row address in response to the clock signal; a byte enable (BE) input adapted to receive a BE signal which enables the burst access memory to output data in a read cycle and to store data in a write cycle, the BE signal also selecting between an access cycle and a refresh cycle; a column address circuit; and a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling said column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling said column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.
Claim 10
Independent Claim
214 words
An apparatus comprising: a burst access memory device adapted to receive a free running clock input signal, said burst access memory device comprising: a plurality of addressable memory data storage cells arranged in rows and columns; a row address strobe (RAS) input adapted to receive a RAS signal which enables a row address latch to receive a row address in response to the clock signal; a byte enable (BE) input adapted to receive a BE signal which enables the burst access memory to output data in a read cycle and to store data in a write cycle, the BE signal also selecting between an access cycle and a refresh cycle; a column address circuit; and a burst control (BC) input adapted to receive a BC signal, a first state of the BC signal enabling said column address circuit to receive a column address in response to the clock signal such that the memory operates in a non-burst mode where column address are provided externally, and a second state of the BC signal enabling said column address circuit to generate additional column addresses in response to the clock signal such that the memory operates in a burst mode, without a separate column address strobe (CAS) signal in both the first state and the second state.
Claim 11
Dependent Claim
17 words
The apparatus according to claim 7, further comprising a microprocessor coupled to said burst access memory device.
Claim 12
Dependent Claim
13 words
The apparatus according to claim 7, wherein the apparatus is a memory module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |