US5956256A — Method and apparatus for optimizing a circuit des…

Claim 1

Independent Claim 158 words

A method for optimizing a circuit design having a number of multi-cycle paths therein, the method comprising the steps of: identifying at least one of the number of multi-cycle paths within the circuit design, wherein each of the identified multi-cycle paths is controlled at least in part by a corresponding qualified clock signal, each of the qualified clock signals being generated by one or more gating blocks that logically combine a corresponding raw clock signal having a raw clock period and a phase with at least one other signal so that the corresponding qualified clock signal has a selectively extendable clock period and phase; replacing selected ones of the qualified clock signals with a corresponding replacement clock signal, wherein each of the replacement clock signals have a clock period and a phase that corresponds to the selectively extendable clock period and phase of the corresponding qualified clock signals; and optimizing the circuit design using selected replacement clock signals.

Claim 2

Independent Claim 158 words

A method for optimizing a circuit design having a number of multi-cycle paths therein, the method comprising the steps of: identifying at least one of the number of multi-cycle paths within the circuit design, wherein each of the identified multi-cycle paths is controlled at least in part by a corresponding qualified clock signal, each of the qualified clock signals being generated by one or more gating blocks that logically combine a corresponding raw clock signal having a raw clock period and a phase with at least one other signal so that the corresponding qualified clock signal has a selectively extendable clock period and phase; replacing selected ones of the qualified clock signals with a corresponding replacement clock signal, wherein each of the replacement clock signals have a clock period and a phase that corresponds to the selectively extendable clock period and phase of the corresponding qualified clock signals; and optimizing the circuit design using selected replacement clock signals.

Claim 3

Dependent Claim 19 words

A method according to claim 1 wherein the optimizing step comprises the initial step of characterizing the circuit design.

Claim 4

Dependent Claim 36 words

A method according to claim 2 wherein the circuit design has a corresponding clock list, and the clock list includes a listing of selected ones of a number of clock signals available to the circuit design.

Claim 5

Dependent Claim 42 words

A method according to claim 3 wherein the circuit design has a number of timing notes associated therewith, wherein selected ones of the number of timing notes indicate the correspondence between the number of clocks signal and the number of multi-cycle paths.

Claim 6

Dependent Claim 21 words

A method according to claim 4 wherein said identifying step identifies the multi-cycle paths by examining the number of timing notes.

Claim 7

Dependent Claim 54 words

A method according to claim 5 wherein said replacing step replaces selected ones of the identified clock signals, in the clock list, with corresponding replacement clock signals by removing the identified clock signals from the clock list and adding the replacement clock signals to the clock list, thereby resulting in an updated clock list.

Claim 8

Dependent Claim 19 words

A method according to claim 6 wherein said characterizing step characterizes the circuit design using the updated clock list.

Claim 9

Dependent Claim 47 words

A method according to claim 7 wherein said characterizing step comprises: performing a timing analysis on the circuit design thereby providing a timing analysis report; and assigning a number of timing constraints to a number of modules within the circuit design by referencing the timing analysis report.

Claim 10

Dependent Claim 32 words

A method according to claim 8 wherein said optimizing step sequentially optimizes selected ones of the number of modules within the circuit design using the timing constraints assigned to the corresponding module.

Claim 11

Independent Claim 171 words

A method for optimizing a circuit design having a number of clock signals wherein some of the number of clock signals are associated with a number of multi-cycle paths, the circuit design having a clock list associated therewith wherein the clock list identifies selected ones of the number of clock signals within the circuit design, the circuit design further having a number of timing notes associated therewith wherein the number of timing notes identify the required clock period of selected ones of the number of multi-cycle paths, the method comprising the steps of: identifying the selected ones of the number of multi-cycle paths, and the associated clock signals, by examining selected ones of the number of timing notes; replacing selected ones of the associated clock signals of the identified multi-cycle paths, in the clock list, with replacement clock signals having a corresponding clock period, thereby providing an updated clock list; characterizing the circuit design using the updated clock list, thereby providing a characterized circuit design; and optimizing the characterized circuit design.

Claim 12

Independent Claim 171 words

A method for optimizing a circuit design having a number of clock signals wherein some of the number of clock signals are associated with a number of multi-cycle paths, the circuit design having a clock list associated therewith wherein the clock list identifies selected ones of the number of clock signals within the circuit design, the circuit design further having a number of timing notes associated therewith wherein the number of timing notes identify the required clock period of selected ones of the number of multi-cycle paths, the method comprising the steps of: identifying the selected ones of the number of multi-cycle paths, and the associated clock signals, by examining selected ones of the number of timing notes; replacing selected ones of the associated clock signals of the identified multi-cycle paths, in the clock list, with replacement clock signals having a corresponding clock period, thereby providing an updated clock list; characterizing the circuit design using the updated clock list, thereby providing a characterized circuit design; and optimizing the characterized circuit design.

Claim 13

Dependent Claim 15 words

A method according to claim 10 wherein the circuit design comprises a number of modules.

Claim 14

Dependent Claim 28 words

A method according to claim 11 wherein selected clock signals associated with a particular multi-cycle path control state devices in two or more of the number of modules.

Claim 15

Dependent Claim 29 words

A method according to claim 12 wherein selected ones of the clock signals are qualified type clock signals generated by gating a clock signal and a functional enable signal.

Claim 16

Independent Claim 142 words

A method for optimizing a circuit design with an optimization tool, wherein the circuit design has a number of qualified clock signals therein, each of the number of qualified clock signals having a first cycle time and a first phase associated therewith and generated by the logical combination of at least a first signal having a second cycle time and a second signal having third cycle time, the method comprising the steps of: identifying at least one of the number of qualified clock signals within the circuit design; replacing selected ones of the identified qualified clock signals with a replacement clock signal, wherein the replacement clock signal has a cycle time and phase that is substantially equal to the first cycle time and the first phase of the corresponding qualified clock signal; and optimizing the circuit design using the replacement clock signal.

Claim 17

Independent Claim 142 words

A method for optimizing a circuit design with an optimization tool, wherein the circuit design has a number of qualified clock signals therein, each of the number of qualified clock signals having a first cycle time and a first phase associated therewith and generated by the logical combination of at least a first signal having a second cycle time and a second signal having third cycle time, the method comprising the steps of: identifying at least one of the number of qualified clock signals within the circuit design; replacing selected ones of the identified qualified clock signals with a replacement clock signal, wherein the replacement clock signal has a cycle time and phase that is substantially equal to the first cycle time and the first phase of the corresponding qualified clock signal; and optimizing the circuit design using the replacement clock signal.

Claim 18

Independent Claim 222 words

A method for optimizing a circuit design with an optimization tool, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the circuit design having a clock file associated therewith which includes an identification of the first clock signal and the second clock signal, the method comprising the steps of: storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; and replacing the second clock signal with a replacement clock signal, wherein the replacement clock signal corresponds to the selected clock pulse of the second clock signal.

Claim 19

Independent Claim 222 words

A method for optimizing a circuit design with an optimization tool, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the circuit design having a clock file associated therewith which includes an identification of the first clock signal and the second clock signal, the method comprising the steps of: storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; and replacing the second clock signal with a replacement clock signal, wherein the replacement clock signal corresponds to the selected clock pulse of the second clock signal.

Claim 20

Dependent Claim 31 words

A method according to claim 15 further comprising the step of: replacing the identification of the second clock signal in the clock file with an identification of the replacement clock signal.

Claim 21

Dependent Claim 121 words

A method according to claim 15 further comprising the steps of: determining a remote propagation time by determining a delay along the path from the source state device to the boundary of the second module; determining a local propagation time by determining a delay along the path from the boundary of the second module to the destination state device; determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the replacement clock signal; determining an allowed local propagation time by subtracting the remote propagation time from the total allowed propagation time; and comparing the allowed local propagation time with the local propagation time.

Claim 22

Independent Claim 283 words

A method for analyzing a circuit design, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the method comprising the steps of: storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; determining a remote propagation time by determining a delay along the path from the source state device to the boundary of the second module; determining a local propagation time by determining a delay along the path from the boundary of the second module to the destination state device; determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the selected clock pulse of the second clock signal; determining an allowed local propagation time by subtracting the remote propagation time from the total allowed propagation time; and comparing the allowed local propagation time with the local propagation time.

Claim 23

Independent Claim 283 words

A method for analyzing a circuit design, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the method comprising the steps of: storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; determining a remote propagation time by determining a delay along the path from the source state device to the boundary of the second module; determining a local propagation time by determining a delay along the path from the boundary of the second module to the destination state device; determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the selected clock pulse of the second clock signal; determining an allowed local propagation time by subtracting the remote propagation time from the total allowed propagation time; and comparing the allowed local propagation time with the local propagation time.

Claim 24

Dependent Claim 34 words

A method according to claim 18 further comprising the step of: optimizing the portion of the path that lies in the second module if the local propagation time exceeds the allowed local propagation time.

Claim 25

Dependent Claim 18 words

A method according to claim 19 wherein the destination state device has a predetermined setup time associated therewith.

Claim 26

Dependent Claim 40 words

A method according to claim 20 wherein said determining step for determining the allowed local propagation time determines the allowed local propagation time by subtracting the remote propagation time and the predetermined setup time from the total allowed propagation time.

Claim 27

Dependent Claim 34 words

A method according to claim 20 wherein said optimizing step optimizes the circuit design if the local propagation time plus the predetermined setup time exceeds the allowed local propagation time by a predetermined amount.

Claim 28

Dependent Claim 24 words

A method according to claim 22 wherein each of said modules has a number of ports, and said path corresponds to an input port.

Claim 29

Dependent Claim 21 words

A method according to claim 23 wherein said storing step stores the selected pulse as an attribute of said input port.

Claim 30

Dependent Claim 22 words

A method according to claim 24 wherein said storing step stores the selected pulse as an attribute of said destination state device.

Claim 31

Dependent Claim 34 words

A method according to claim 18 further comprising the step of: optimizing the portion of the path that lies in the first module if the local propagation time exceeds the allowed local propagation time.

Claim 32

Dependent Claim 18 words

A method according to claim 26 wherein the destination state device has a predetermined setup time associated therewith.

Claim 33

Dependent Claim 40 words

A method according to claim 27 wherein said determining step for determining the total allowed propagation time determines the allowed local propagation time by subtracting the remote propagation time and the predetermined setup time from the total allowed propagation time.

Claim 34

Independent Claim 422 words

A method for optimizing a circuit design with an optimization tool, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the method comprising the steps of: storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; determining a first propagation time by determining a delay along the path from the source state device to the boundary of the second module; determining a second propagation time by determining a delay along the path from the boundary of the second module to the destination state device; determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the selected clock pulse of the second clock signal; adding the first propagation time and the second propagation time, thereby resulting in a total propagation time for the path; comparing the total propagation time and the total allowed propagation time to determine if the total propagation time is within a predetermined specification of the total allowed propagation time; allocating a desired first optimization amount to the first module and a desired second optimization amount to the second module if the total propagation time is not within the predetermined specification of the total allowed propagation time; optimizing the portion of the path within the first module to reduce the first propagation time by the desired first optimization amount, if the total propagation time is not within the predetermined specification of the total allowed propagation time; and optimizing the portion of the path within the second module to reduce the second propagation time by the desired second optimization amount, if the total propagation time is not within the predetermined specification of the total allowed propagation time.

Claim 35

Independent Claim 422 words

A method for optimizing a circuit design with an optimization tool, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the method comprising the steps of: storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; determining a first propagation time by determining a delay along the path from the source state device to the boundary of the second module; determining a second propagation time by determining a delay along the path from the boundary of the second module to the destination state device; determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the selected clock pulse of the second clock signal; adding the first propagation time and the second propagation time, thereby resulting in a total propagation time for the path; comparing the total propagation time and the total allowed propagation time to determine if the total propagation time is within a predetermined specification of the total allowed propagation time; allocating a desired first optimization amount to the first module and a desired second optimization amount to the second module if the total propagation time is not within the predetermined specification of the total allowed propagation time; optimizing the portion of the path within the first module to reduce the first propagation time by the desired first optimization amount, if the total propagation time is not within the predetermined specification of the total allowed propagation time; and optimizing the portion of the path within the second module to reduce the second propagation time by the desired second optimization amount, if the total propagation time is not within the predetermined specification of the total allowed propagation time.

Claim 36

Dependent Claim 185 words

Apparatus for optimizing a circuit design having a number of multi-cycle paths therein, wherein each of the multi-cycle paths has a number of corresponding clock signals associated therewith, comprising: identifying means for identifying at least one of the number of multi-cycle paths within the circuit design, each of the identified multi-cycle paths being controlled at least in part by a corresponding qualified clock signal, each of the qualified clock signals being generated by one or more gating blocks that logically combine a corresponding raw clock signal having a raw clock period and a phase with at least one other signal so that the corresponding qualified clock signal has a selectively extendable clock period and phase; replacing means coupled to said identifying means for replacing selected ones of the qualified clock signals with a corresponding replacement clock signal, wherein each of the replacement clock signals have a clock period and a phase that corresponds to the selectively extendable clock period and phase of the corresponding qualified clock signals; and optimizing means coupled to said replacing means for optimizing the circuit design using selected replacement clock signals.

Claim 37

Dependent Claim 185 words

Apparatus for optimizing a circuit design having a number of multi-cycle paths therein, wherein each of the multi-cycle paths has a number of corresponding clock signals associated therewith, comprising: identifying means for identifying at least one of the number of multi-cycle paths within the circuit design, each of the identified multi-cycle paths being controlled at least in part by a corresponding qualified clock signal, each of the qualified clock signals being generated by one or more gating blocks that logically combine a corresponding raw clock signal having a raw clock period and a phase with at least one other signal so that the corresponding qualified clock signal has a selectively extendable clock period and phase; replacing means coupled to said identifying means for replacing selected ones of the qualified clock signals with a corresponding replacement clock signal, wherein each of the replacement clock signals have a clock period and a phase that corresponds to the selectively extendable clock period and phase of the corresponding qualified clock signals; and optimizing means coupled to said replacing means for optimizing the circuit design using selected replacement clock signals.

Claim 38

Dependent Claim 26 words

Apparatus according to claim 30 wherein said optimizing means further comprises characterizing means for characterizing the circuit design prior to the optimization of the circuit design.

Claim 39

Dependent Claim 461 words

Apparatus for optimizing a circuit design, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the method comprising the steps of: storing means for storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; first determining means for determining a first propagation time by determining a delay along the path from the source state device to the boundary of the second module; second determining means for determining a second propagation time by determining a delay along the path from the boundary of the second module to the destination state device; third determining means for determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the selected clock pulse of the second clock signal; adding means coupled to said first determining means and to said second determining means for adding the first propagation time and the second propagation time, thereby resulting in a total propagation time for the path; comparing means coupled to said adding means and to said third determining means for comparing the total propagation time and the total allowed propagation time to determine if the total propagation time is within a predetermined specification of the total allowed propagation time; allocating means coupled to said comparing means for allocating a desired first optimization amount to the first module and a desired second optimization amount to the second module if the total propagation time is not within the predetermined specification of the total allowed propagation time; optimizing means coupled to said allocating means for optimizing the portion of the path within the first module to reduce the first propagation time by the desired first optimization amount, and for optimizing the portion of the path within the second module to reduce the second propagation time by the desired second optimization amount, if the total propagation time is not within the predetermined specification of the total allowed propagation time.

Claim 40

Dependent Claim 461 words

Apparatus for optimizing a circuit design, wherein the circuit design has a number of modules and each of the modules has a boundary, each of the modules further having a number of state devices, the circuit design having a source state device in a first module and a destination state device in a second module wherein the source state device provides data to the destination state device through a path, the source state device being clocked by a first clock signal having a clock pulse and the destination state device being clocked by a second clock signal having a number of clock pulses, the method comprising the steps of: storing means for storing a number of timing constraints wherein the number of timing constraints associate a selected clock pulse of the second clock signal with the path, the selected clock pulse corresponding to the clock pulse of the second clock signal by which the data provided by the source state device is required to arrive at the destination state device; first determining means for determining a first propagation time by determining a delay along the path from the source state device to the boundary of the second module; second determining means for determining a second propagation time by determining a delay along the path from the boundary of the second module to the destination state device; third determining means for determining a total allowed propagation time by determining a delay between a predetermined portion of the clock pulse of the first clock signal and a predetermined portion of the selected clock pulse of the second clock signal; adding means coupled to said first determining means and to said second determining means for adding the first propagation time and the second propagation time, thereby resulting in a total propagation time for the path; comparing means coupled to said adding means and to said third determining means for comparing the total propagation time and the total allowed propagation time to determine if the total propagation time is within a predetermined specification of the total allowed propagation time; allocating means coupled to said comparing means for allocating a desired first optimization amount to the first module and a desired second optimization amount to the second module if the total propagation time is not within the predetermined specification of the total allowed propagation time; optimizing means coupled to said allocating means for optimizing the portion of the path within the first module to reduce the first propagation time by the desired first optimization amount, and for optimizing the portion of the path within the second module to reduce the second propagation time by the desired second optimization amount, if the total propagation time is not within the predetermined specification of the total allowed propagation time.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-09-20	2003-03-22	2003-09-21	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-09-20	2007-03-22	2007-09-21	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-09-20	2011-03-22	2011-09-21	$7700.00	Window Closed / Lapsed

Method and apparatus for optimizing a circuit design having multi-paths therein

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