US5517638A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic clock switching circuitry and method
Assignee: Texas Instruments Inc
•
Filing: 1993-05-13
•
Granted: 1996-05-14
•
Expires: 2013-05-13
Abstract
Abstract Circuitry for switching between a first and second clock signal is provided having a first local clock circuit 202, a first synchronizing circuit 200 connected to said first clock circuit 202, a first delay circuit 206a-d connected to said first synchronizing circuit 200 and said first clock circuit 202, a second delay circuit 206e, 210, connected to said first delay circuit 206a-d and said first clock circuit 202, a first logic circuit 220 connected to said first 206a-d and second 206e, 210 delay circuits and said first synchronizing circuit 200, a second local clock circuit 102, a second synchronizing circuit 100 connected to said second clock circuit 102, a third delay circuit 106, 108, 110, connected to said second synchronizing circuit 100 and said second clock circuit 102, a second logic circuit 104 connected to said second clock circuit 102 and a portion of said third delay circuit 106, 108, 110, a third logic circuit 120 connected to said third delay circuit 106, 108, 110, and said second clock circuit 102, and a multiplexer 16 connected to said first 220 and third 120 logic circuits. The method of the present invention switches between a first 19 and second 21 clock signal by detecting a change in a signal 23 indicative of need to switch from said first clock signal to said second clock signal (or vice vers. a) 302, generating at least one local control signal 70, 72 responsive to said detection 304, deselecting a first in use clock signal 306 responsive to a first local control signal, selecting the second clock signal 308 for use responsive to a second local control signal, and switching to the non-used (second) clock signal after a preselected delay 310 based upon said second clock signal and said detection of said change in said signal.
Inventors
- 👤 Andre Szczepanek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:38
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
513 words
An apparatus for switching between a first clock signal and a second clock signal, said first clock signal continuously oscillating between a first digital state and a second digital state, said second clock signal intermittently oscillating between said first digital state and said second digital state, said first and second clock signals having approximately the same frequency and being asynchronous, said apparatus comprising: a multiplexer having a first clock input receiving said first clock signal, a second clock input receiving said second clock signal, a first control input, a second control input and an output, said multiplexer coupling said first clock signal to said output upon receipt of a signal having said first digital state at said first control input and coupling said second clock signal to said output upon receipt of a signal having said first digital state at said second control input; a first clock block having a first clock input receiving said first clock signal, a first control input receiving a first active signal having said second digital state when said second clock signal is oscillating and a first control output connected to said first control input of said multiplexer, said first clock block including a first delay circuit connected to said control input, said first delay circuit generating a first delay signal at said first digital state a first predetermined time after said first active signal received at said control input changes from said second digital state to said first digital state, a first clock block output circuit connected to said first clock input, said first control output and said first delay circuit, said first clock block output circuit generating a first control signal on said first control output having said first digital state when said first clock signal has said second state following generation of said first delay signal; and a second clock block having a second clock input receiving said second clock signal, a second control input receiving a second active signal having said first digital state when said second clock signal is oscillating and a second control output connected to said second control input of said multiplexer, said second clock block including a second delay circuit connected to said second control input and said second control output, said second delay circuit generating a signal on said second control output at said first digital state a second predetermined time after said second active signal received at said control input changes from said second digital state to said first digital state, a feedback logic circuit connected to said first control output of said first clock block latching said first control signal, a second clock block output circuit connected to said second clock input, said second control output, said second delay circuit and said feedback logic circuit, said second clock block output circuit generating an output on said second control output having said first digital state when 1) said second clock signal has said second state following generation of said first delay signal, and 2) said first control signal latched in said feedback logic circuit has said second state.
Claim 2
Independent Claim
513 words
An apparatus for switching between a first clock signal and a second clock signal, said first clock signal continuously oscillating between a first digital state and a second digital state, said second clock signal intermittently oscillating between said first digital state and said second digital state, said first and second clock signals having approximately the same frequency and being asynchronous, said apparatus comprising: a multiplexer having a first clock input receiving said first clock signal, a second clock input receiving said second clock signal, a first control input, a second control input and an output, said multiplexer coupling said first clock signal to said output upon receipt of a signal having said first digital state at said first control input and coupling said second clock signal to said output upon receipt of a signal having said first digital state at said second control input; a first clock block having a first clock input receiving said first clock signal, a first control input receiving a first active signal having said second digital state when said second clock signal is oscillating and a first control output connected to said first control input of said multiplexer, said first clock block including a first delay circuit connected to said control input, said first delay circuit generating a first delay signal at said first digital state a first predetermined time after said first active signal received at said control input changes from said second digital state to said first digital state, a first clock block output circuit connected to said first clock input, said first control output and said first delay circuit, said first clock block output circuit generating a first control signal on said first control output having said first digital state when said first clock signal has said second state following generation of said first delay signal; and a second clock block having a second clock input receiving said second clock signal, a second control input receiving a second active signal having said first digital state when said second clock signal is oscillating and a second control output connected to said second control input of said multiplexer, said second clock block including a second delay circuit connected to said second control input and said second control output, said second delay circuit generating a signal on said second control output at said first digital state a second predetermined time after said second active signal received at said control input changes from said second digital state to said first digital state, a feedback logic circuit connected to said first control output of said first clock block latching said first control signal, a second clock block output circuit connected to said second clock input, said second control output, said second delay circuit and said feedback logic circuit, said second clock block output circuit generating an output on said second control output having said first digital state when 1) said second clock signal has said second state following generation of said first delay signal, and 2) said first control signal latched in said feedback logic circuit has said second state.
Claim 3
Dependent Claim
19 words
The apparatus of claim 1, wherein: said first predetermined time is two clock cycles of said first clock signal.
Claim 4
Dependent Claim
19 words
The apparatus of claim 1, wherein: said second predetermined time is two clock cycles of said second clock signal.
Claim 5
Dependent Claim
89 words
The apparatus of claim 1, wherein: said first delay circuit includes a first local clock generator connected to said first clock input generating a first in-phase local clock signal in phase with said first clock signal and a first out-of-phase local clock signal having a phase opposite to said first clock signal, and a first chain of a plurality of delay latches connected to said first local clock generator forming a clocked delay line clocked by said first in-phase local clock signal and said first out-of-phase local clock signal.
Claim 6
Dependent Claim
135 words
The apparatus of claim 1, wherein: said second delay circuit includes a second local clock generator connected to said second clock input generating a second in-phase local clock signal in phase with said second clock signal and a second out-of-phase local clock signal having a phase opposite to said second clock signal, and a second chain of a plurality of delay latches connected to said feedback logic circuit and said second local clock generator, said second chain of a plurality of delay latches forming a clocked delay line clocked by said second in-phase local clock signal and said second out-of-phase local clock signal, each latch of said second chain of a plurality of delay latches cleared to a predetermined state when said first control signal latched in said feedback logic circuit has said first state.
Claim 7
Dependent Claim
107 words
The apparatus of claim 1, wherein: said first clock block further includes a third delay circuit connected to said first delay circuit generating a third delay signal at said first digital state a third predetermined time after said first delay signal changes from said second digital state to said first digital state, and said first clock block output circuit is further connected to said third delay circuit, said first clock block output circuit generating said first control signal on said first control output having said second digital state only after said third delay signal has been received following said first active signal having said second digital state.
Claim 8
Independent Claim
203 words
A method for switching between a first clock signal continuously oscillating between a first digital state and a second digital state, and a second clock signal intermittently oscillating between said first digital state and said second digital state based upon a control signal having a first digital state when said second clock signal is oscillating, said first and second clock signals having approximately the same frequency and being asynchronous, said method comprising the steps of: deselecting said first clock signal a first predetermined time following said control signal changing from said first digital state to said second digital state; selecting said second clock signal during a next interval when said second clock signal is in said second digital state following a second predetermined time after said control signal changes from said first digital state to said second digital state; deselecting said second clock signal said second predetermined time following said control signal changing from said second digital state to said first digital state; selecting said first clock signal during a next interval when said first clock signal is in said second digital state following said first predetermined time after said control signal changes from said second digital state to said first digital state.
Claim 9
Independent Claim
203 words
A method for switching between a first clock signal continuously oscillating between a first digital state and a second digital state, and a second clock signal intermittently oscillating between said first digital state and said second digital state based upon a control signal having a first digital state when said second clock signal is oscillating, said first and second clock signals having approximately the same frequency and being asynchronous, said method comprising the steps of: deselecting said first clock signal a first predetermined time following said control signal changing from said first digital state to said second digital state; selecting said second clock signal during a next interval when said second clock signal is in said second digital state following a second predetermined time after said control signal changes from said first digital state to said second digital state; deselecting said second clock signal said second predetermined time following said control signal changing from said second digital state to said first digital state; selecting said first clock signal during a next interval when said first clock signal is in said second digital state following said first predetermined time after said control signal changes from said second digital state to said first digital state.
Claim 10
Dependent Claim
38 words
The method of claim 7, wherein: said step of deselecting said first clock signal further includes continuing to select said first clock signal unit said first clock signal has been selected for at least a third predetermined time.
References Cited (Backward Citations)
US4511993A
Cited
US4398155A
Cited
US4696019A
Cited
US4651103A
Cited
US4841523A
Cited
US4823262A
Cited
US4866703A
Cited
US4870299A
Cited
US5241543A
Cited
US5287025A
Cited
US5274678A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-14 | 1999-11-13 | 2000-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-14 | 2003-11-13 | 2004-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-14 | 2007-11-13 | 2008-05-14 | $7700.00 | Window Closed / Lapsed |