Floor-planning apparatus for hierarchical design of LSI

Claim 1

A floor-planning apparatus for a hierarchical design of a large scale integrated circuit (LSI) comprising: means for storing information regarding a logic circuit interconnection of the LSI, grouping information regarding groups of function blocks which can be functionally grouped as function units and macro information of macros used in the hierarchical design of the LSI; means for disposing the macros and the groups by using the macro information and the grouping information; display means for displaying a disposition of the macros and groups; means for grouping the function blocks for each function unit as macro groups according to an external request; means for displaying as a rats net the interconnecting relationship between the macros, groups and macro groups to achieve a better disposition thereof, upon receipt of a modifying direction; means for schematically interconnecting between the macro groups after the macros and the groups have been disposed; means for calculating a schematic wiring length between the macro groups for evaluating the wiring length of the schematic wiring; and means for replacing a function block at an output side of one of the macros and the macro groups connected through the schematic wiring having a length longer than a predetermined length by a function block used for high duty driving.

Claim 5

A method of performing a hierarchial design of a floor plan for a large scale integrated circuit (LSI), comprising the steps of: holding in a memory, logic circuit interconnection data of the LSI, grouping data indicating function blocks which can be grouped and macro data of macros; disposing the macros and the function blocks using the grouping data and the macro data held in the memory; displaying the disposition of the macros and the function blocks; grouping the function blocks in response to an external command into function block macro groups; producing and displaying a rats net interconnecting relationship of the function block macro groups and the macros; rearranging, in response to an external command, a disposition of the function block macro groups and the macros to enhance the disposition thereof; schematically interconnecting the function block macro groups and the macros; calculating a schematic wiring length between function block macro groups; and replacing an output side function block of a function block macro group with a new function block having a high duty driving capacity when the output side function block has an interconnection to another element in the floor plan using a schematic wiring having a length which exceeds a predetermined length.

Claim 6

A method of performing a hierarchial design of a floor plan for a large scale integrated circuit (LSI), comprising the steps of: holding in a memory, logic circuit interconnection data of the LSI, grouping data indicating function blocks which can be grouped and macro data of macros; disposing the macros and the function blocks using the grouping data and the macro data held in the memory; displaying the disposition of the macros and the function blocks; grouping the function blocks in response to an external command into function block macro groups; producing and displaying a rats net interconnecting relationship of the function block macro groups and the macros; rearranging, in response to an external command, a disposition of the function block macro groups and the macros to enhance the disposition thereof; schematically interconnecting the function block macro groups and the macros; calculating a schematic wiring length between function block macro groups; and replacing an output side function block of a function block macro group with a new function block having a high duty driving capacity when the output side function block has an interconnection to another element in the floor plan using a schematic wiring having a length which exceeds a predetermined length.