US5644499A
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Retiming gated-clocks and precharged circuit structures
Assignee: NEC Corp
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Filing: 1995-09-07
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Granted: 1997-07-01
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Expires: 2015-09-07
Abstract
Abstract A general set of timing constraints, along with methods for computing the "critical" elements of the set, i.e., the elements of the set that, if satisfied, are sufficient to guarantee proper circuit timing, enables retiming of VLSI systems incorporating gated clock signals and/or precharged circuit structures without changing the input/output behavior of the system. In one method, either the clock signal used by a system component is changed or alternatively, a new clock signal is generated for use in the system. In another method, a system component is retimed by retiming other system components. In a further method, multiple critical paths for each pair of components comprising the system are computed. The most critical path for each pair of components is selected and if the most critical path for a pair of components is not properly timed, one component of the pair is retimed in order to properly time the pair of components. If the most critical path is properly timed, or is properly timed after retiming, the procedure is repeated for another pair of components until each pair of components is properly timed so that the VLSI system is, in turn, retimed.
Inventors
- 👤 Alexander T. Ishii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:29
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
106 words
A method of designing a VLSI system including precharged circuit structures by virtue of gated clock signals and having a set of timing constraints, comprising the steps of: determining critical elements of the set of timing constraints; formulating sets of inequalities between the delay of a path and the temporal length of a critical path bounded by a pair of clock edges based upon said critical elements; selecting clock signals for use in the delay path for a set of inequalities, which clock signals retime the VLS1 system without changing the input/output behavior of the system; and designing said system based on said selected clock signals.
Claim 2
Independent Claim
106 words
A method of designing a VLSI system including precharged circuit structures by virtue of gated clock signals and having a set of timing constraints, comprising the steps of: determining critical elements of the set of timing constraints; formulating sets of inequalities between the delay of a path and the temporal length of a critical path bounded by a pair of clock edges based upon said critical elements; selecting clock signals for use in the delay path for a set of inequalities, which clock signals retime the VLS1 system without changing the input/output behavior of the system; and designing said system based on said selected clock signals.
Claim 3
Dependent Claim
24 words
A method of designing a VLSI system as set forth in claim 1, wherein said selecting clock signals comprises selecting alternatively available clock signals.
Claim 4
Dependent Claim
25 words
A method of designing a VLSI system as set forth in claim 1, wherein said selecting clock signals comprises selecting a new generated clock signal.
Claim 5
Dependent Claim
23 words
A method of designing a VLSI system as set forth in claim 1, further comprising determining critical timing constraints for each clock signal.
Claim 6
Dependent Claim
53 words
A method of designing a VLSI system as set forth in claim 1, wherein said timing constraints are d(p)≦τ.sub.ΦΦ' (p) where p=uv, d(p) is the total propagation delay along p, Φ is an input phase of u,Φ' is an output phase of v and τ.sub.ΦΦ' (p) is the ΦΦ' temporal length of p.
Claim 7
Independent Claim
261 words
A method of designing a VLSI system having a level-clocked circuit represented as a directed multi-graph G=(V,E,d,Φ I ,Φ O ), where delay function d maps the element of V to nonnegative real numbers, the input phase function Φ I maps each element V to an output phase set, and the output phase function Φ O maps each element of V to an output phase set and E is a set of edges, comprising the steps of: computing a retiming function r: V→Z, where V is the set of components and Z is the of integers such that for path p and input-output phase combination χ i -χ j ; ##EQU4## where (δ) is the length of time between χ k and χ k+1 and the subscript is modulo-4 and χ 0 , χ 1 , χ 2 and χ 3 denote rising edge of clock φ O , the falling edge of clock φ O , the rising edge of clock φ 1 , and the falling edge of clock φ 1 respectively, τ.sub.χiχi (p) is the temporal length and d(p) is the propagation delay along path p, and retiming function values r(u)=r(v) for all components v and components u such that (u→v)εE and a lagged version of the signal represented by u cannot be obtained with the introduction of a latch whose data input is u; lagging u and v by selecting input phase functions and output phase functions for retiming the VLSI system according to the calculated retiming function values; and designing said systems based upon said lagging.
Claim 8
Independent Claim
261 words
A method of designing a VLSI system having a level-clocked circuit represented as a directed multi-graph G=(V,E,d,Φ I ,Φ O ), where delay function d maps the element of V to nonnegative real numbers, the input phase function Φ I maps each element V to an output phase set, and the output phase function Φ O maps each element of V to an output phase set and E is a set of edges, comprising the steps of: computing a retiming function r: V→Z, where V is the set of components and Z is the of integers such that for path p and input-output phase combination χ i -χ j ; ##EQU4## where (δ) is the length of time between χ k and χ k+1 and the subscript is modulo-4 and χ 0 , χ 1 , χ 2 and χ 3 denote rising edge of clock φ O , the falling edge of clock φ O , the rising edge of clock φ 1 , and the falling edge of clock φ 1 respectively, τ.sub.χiχi (p) is the temporal length and d(p) is the propagation delay along path p, and retiming function values r(u)=r(v) for all components v and components u such that (u→v)εE and a lagged version of the signal represented by u cannot be obtained with the introduction of a latch whose data input is u; lagging u and v by selecting input phase functions and output phase functions for retiming the VLSI system according to the calculated retiming function values; and designing said systems based upon said lagging.
Claim 9
Dependent Claim
19 words
A method as set forth in claim 6, wherein said input phase and said output phase are clock edges.
Claim 10
Dependent Claim
16 words
A method as set forth in claim 7, wherein said lagging comprises selecting a clock signal.
Claim 11
Dependent Claim
18 words
A method as set forth in claim 7, wherein said lagging comprises selecting a newly generated clock signal.
Claim 12
Independent Claim
138 words
A method of designing a VLSI system, the system having multiple components, each component having input phases and output phases, comprising the steps of: (a) computing a critical path for each pair of components and each pair of input phases and output phases for the pair of components; (b) selecting for each pair of components a most critical path; (c) if the most critical path is not properly timed, retime one component of the pair of components by use of a selected input phase or output phase to properly time the path; (d) if the most critical path is properly timed or after step (c), repeat steps (b) and (c) until each most critical path between each pair of components is properly timed; and (e) designing said system based on said each most critical path being properly timed.
Claim 13
Independent Claim
138 words
A method of designing a VLSI system, the system having multiple components, each component having input phases and output phases, comprising the steps of: (a) computing a critical path for each pair of components and each pair of input phases and output phases for the pair of components; (b) selecting for each pair of components a most critical path; (c) if the most critical path is not properly timed, retime one component of the pair of components by use of a selected input phase or output phase to properly time the path; (d) if the most critical path is properly timed or after step (c), repeat steps (b) and (c) until each most critical path between each pair of components is properly timed; and (e) designing said system based on said each most critical path being properly timed.
Claim 14
Independent Claim
118 words
A method of a VLSI system containing components having multiple input phases and/or multiple output phases and multiple temporal lengths for each combination of input phase and output phase comprising the steps of: computing critical paths between a predetermined input phase and each output phase, where said input phase and said output phase are clock edges; determining the shortest critical path computed; calculating retiming functions values r(u) and r(v) for the shortest critical path; lagging u and v the quantity of times determined by said retiming function values by selecting input phases and output phases in the shortest critical path, where u and v are components of the VLSI system; and designing said system based on said lagging.
Claim 15
Independent Claim
118 words
A method of a VLSI system containing components having multiple input phases and/or multiple output phases and multiple temporal lengths for each combination of input phase and output phase comprising the steps of: computing critical paths between a predetermined input phase and each output phase, where said input phase and said output phase are clock edges; determining the shortest critical path computed; calculating retiming functions values r(u) and r(v) for the shortest critical path; lagging u and v the quantity of times determined by said retiming function values by selecting input phases and output phases in the shortest critical path, where u and v are components of the VLSI system; and designing said system based on said lagging.
Claim 16
Dependent Claim
21 words
A method of designing a VLSI system as set forth in claim 11 where said lagging comprises changing a clock input.
Claim 17
Dependent Claim
22 words
A method of designing a VLSI system as set forth in claim 11 where said lagging comprises using a new clock input.
Claim 18
Dependent Claim
29 words
A method of designing a VLSI system as set forth in claim 11, wherein said lagging comprises lagging all of the outputs of selected components of the VLSI system.
Claim 19
Dependent Claim
21 words
A method of designing a VLSI system as set forth in claim 11, wherein said lagging comprises selecting a clock signal.
Claim 20
Dependent Claim
22 words
A method of designing a VLSI system as set forth in claim 11, wherein said lagging comprises selecting a newly-generated clock signal.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |