US5448497A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Exploiting multi-cycle false paths in the performance optimization of sequential circuits
Assignee: NEC Corp
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Filing: 1992-09-08
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Granted: 1995-09-05
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Expires: 2012-09-08
Abstract
Abstract A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.
Inventors
- 👤 Pranav Ashar
- 👤 Sujit Dey
- 👤 Sharad Malik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:20
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
168 words
The process for redesigning a sequential circuit that includes memory elements to reduce its delay without affecting its operating function comprising the steps of preparing from a design of the sequential circuit a design in which the sequential circuit is cascaded over a plurality of time frames to provide a cascaded circuit design with the memory elements of the circuit absent, doing a timing analysis of the cascaded circuit design to identify the length L in time of the longest true path in the cascaded circuit, and therefrom to identify any false paths of length in time longer than L, reconfiguring the initial sequential circuit design to remove paths that are longer than L in time over the plurality of time frames without affecting the functionality of the circuit, removing any combinational or sequential redundancies from the reconfigured sequential circuit design, and retiming the resulting circuit design by repositioning memory elements of the circuit for reducing any unnecessary delay, thereby providing the desired circuit design with reduced delay.
Claim 2
Dependent Claim
168 words
The process for redesigning a sequential circuit that includes memory elements to reduce its delay without affecting its operating function comprising the steps of preparing from a design of the sequential circuit a design in which the sequential circuit is cascaded over a plurality of time frames to provide a cascaded circuit design with the memory elements of the circuit absent, doing a timing analysis of the cascaded circuit design to identify the length L in time of the longest true path in the cascaded circuit, and therefrom to identify any false paths of length in time longer than L, reconfiguring the initial sequential circuit design to remove paths that are longer than L in time over the plurality of time frames without affecting the functionality of the circuit, removing any combinational or sequential redundancies from the reconfigured sequential circuit design, and retiming the resulting circuit design by repositioning memory elements of the circuit for reducing any unnecessary delay, thereby providing the desired circuit design with reduced delay.
Claim 3
Dependent Claim
47 words
The process for claim 1 in which the step of reconfiguring the initial sequential circuit includes providing for gates involving fanout that are included in said false paths of length longer than L an alternate path independent of false paths to preserve the functionality of the circuit.
Claim 4
Dependent Claim
20 words
The process of claim 1 in which the sequential circuit to be redesigned is free of any multi-cycle combinational paths.
Claim 5
Dependent Claim
163 words
The process for redesigning a sequential circuit that includes memory elements to reduce its delay without affecting its operating function comprising the steps of preparing from a design of the sequential circuit a design in which the sequential circuit is cascaded over a plurality of time frames to provide a cascaded circuit design with the memory elements of the circuit absent, doing a timing analysis of the cascaded circuit design to identify the length L in time of the longest true path in the cascaded circuit, and therefrom to identify any false paths of length in time longer than L, reconfiguring the inital sequential circuit design to remove paths that are longer than L in time over the plurality of time frames without affecting the functionality of the circuit, retiming the resulting circuit design for reducing any unnecessary delay in its design, thereby providing the desired circuit with reduced delay, and removing any combinational or sequential redundancies from the reconfigured sequential circuit design.
Claim 6
Dependent Claim
163 words
The process for redesigning a sequential circuit that includes memory elements to reduce its delay without affecting its operating function comprising the steps of preparing from a design of the sequential circuit a design in which the sequential circuit is cascaded over a plurality of time frames to provide a cascaded circuit design with the memory elements of the circuit absent, doing a timing analysis of the cascaded circuit design to identify the length L in time of the longest true path in the cascaded circuit, and therefrom to identify any false paths of length in time longer than L, reconfiguring the inital sequential circuit design to remove paths that are longer than L in time over the plurality of time frames without affecting the functionality of the circuit, retiming the resulting circuit design for reducing any unnecessary delay in its design, thereby providing the desired circuit with reduced delay, and removing any combinational or sequential redundancies from the reconfigured sequential circuit design.
Claim 7
Dependent Claim
20 words
The process of claim 4 in which the sequential circuit to be redesigned is free of any multi-cycle combinational paths.
Claim 8
Dependent Claim
47 words
The process for claim 4 in which the step of reconfiguring the initial sequential circuit includes providing for gates involving fanout that are included in said false paths of length longer than L an alternate path independent of false paths to preserve the functionality of the circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |