Automatic logic model generation from schematic data base

Claim 1

An automatic model generation system for automating logic and timing model generation, comprising: an integrated circuit design station including: a computer, a graphic display device displaying signals generated by the computer, a graphic input device for making inputs to the computer, schematic capture software in the computer for operating on the inputs and storing in the computer a net-list interconnection representation of a graphical representation of a circuit, simulation stimulus generation software in the computer for providing stimulus data corresponding to patterns of input stimuli for the circuit; logic simulation software in the computer for simulating performance of a logic-level model of the circuit according to the stimulus data and for providing logic simulation results, said logic-level model of the circuit being represented as interconnected logic blocks, and circuit-level simulation software in the computer for simulating performance of a transistor-level model of the circuit according to the stimulus data and for providing simulated performance results; means in the computer for providing layout information to the transistor-level model of the circuit; and means in the computer for providing timing and delay information obtained from the simulated performance of transistor-level simulation to the logic blocks used in the simulation of the logic-level model.