US5940609A — Synchronous clock generator including a false loc…

Claim 1

Independent Claim 97 words

A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal, comprising: a delay line included in said locked loop, said delay line producing a signal at a 90° tap thereof; and a logic circuit including a flip-flop connected to receive the signal from the 90° tap and the clock signal, said logic circuit for determining if a predetermined phase relationship exists between the signal from the 90° tap and the clock signal and for producing an output signal indicative of said determination.

Claim 2

Dependent Claim 97 words

A false lock detector for use in conjunction with a locked loop which produces a plurality of output signals in response to a clock signal, comprising: a delay line included in said locked loop, said delay line producing a signal at a 90° tap thereof; and a logic circuit including a flip-flop connected to receive the signal from the 90° tap and the clock signal, said logic circuit for determining if a predetermined phase relationship exists between the signal from the 90° tap and the clock signal and for producing an output signal indicative of said determination.

Claim 3

Dependent Claim 120 words

A false lock detector for use with a delay-locked loop which produces a plurality of output signals in response to a clock signal, comprising: a delay line included in said delay-locked loop, said delay line producing a signal at a 90° tap thereof; and a logic circuit connected to receive first and second signals produced by the delay-locked loop, said logic circuit including a flip-flop connected to receive the signal from the 90° tap and the clock signal, said signal from the 90° tap having known states when said clock signal changes states, said logic circuit producing an output signal indicative of whether said signal from the 90° tap is in said known states when said clock signal changes states.

Claim 4

Dependent Claim 120 words

A false lock detector for use with a delay-locked loop which produces a plurality of output signals in response to a clock signal, comprising: a delay line included in said delay-locked loop, said delay line producing a signal at a 90° tap thereof; and a logic circuit connected to receive first and second signals produced by the delay-locked loop, said logic circuit including a flip-flop connected to receive the signal from the 90° tap and the clock signal, said signal from the 90° tap having known states when said clock signal changes states, said logic circuit producing an output signal indicative of whether said signal from the 90° tap is in said known states when said clock signal changes states.

Claim 5

Dependent Claim 100 words

A delay-locked loop having a false lock detector, comprising: a delay line for receiving a clock signal and for producing a plurality of output signals each having a predetermined delay with respect to the clock signal; a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; and a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

Claim 6

Dependent Claim 100 words

A delay-locked loop having a false lock detector, comprising: a delay line for receiving a clock signal and for producing a plurality of output signals each having a predetermined delay with respect to the clock signal; a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; and a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

Claim 7

Dependent Claim 43 words

The delay-locked loop of claim 3 wherein said feedback path comprises a phase detector responsive to certain of said plurality of output signals and a charge pump responsive to said phase detector, and wherein said output signal is input to said phase detector.

Claim 8

Dependent Claim 129 words

A synchronous clock generator having a false lock detector, comprising: a receiver for receiving an external clock signal; a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal; a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

Claim 9

Dependent Claim 129 words

A synchronous clock generator having a false lock detector, comprising: a receiver for receiving an external clock signal; a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal; a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

Claim 10

Dependent Claim 44 words

The synchronous clock generator of claim 5 wherein said feedback path comprises a phase detector responsive to certain of said plurality of output signals and a charge pump responsive to said phase detector, and wherein said output signal is input to said phase detector.

Claim 11

Independent Claim 165 words

A system, comprising: a processor; a memory controller; a plurality of memory devices, a first bus interconnecting said processor and said memory controller; and a second bus interconnecting said memory controller and said memory devices; each of said memory devices having a synchronous clock generator, comprising: a receiver for receiving an external clock signal; a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal; a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

Claim 12

Independent Claim 165 words

A system, comprising: a processor; a memory controller; a plurality of memory devices, a first bus interconnecting said processor and said memory controller; and a second bus interconnecting said memory controller and said memory devices; each of said memory devices having a synchronous clock generator, comprising: a receiver for receiving an external clock signal; a delay line responsive to said receiver for producing a plurality of output signals each having a predetermined delay with respect to the external clock signal; a feedback path responsive to certain of the plurality of output signals for producing a feedback signal input to said delay line; a plurality of multiplexers responsive to said delay line for producing at least one clock signal in response to control signals; and a logic circuit for receiving first and second signals produced by said delay line, said logic circuit for determining if a predetermined phase relationship exists between the first and second signals and for producing an output signal indicative of said determination.

Claim 13

Dependent Claim 200 words

An internal clock generator circuit, comprising: a clock generator including a locked loop constructed to provide first and second internal clock signals, the first clock signal having a phase determined by first and second phase control signals applied to respective first and second control inputs of the clock generator; a phase detector coupled to the clock generator to receive the first internal clock signal, the phase detector further receiving a reference clock signal, the phase detector being constructed to generate an output signal indicative of the phase of the first internal clock signal relative to the phase of the reference clock signal, the output signal being coupled to the first control input of the clock generator; and a false lock detector coupled to the clock generator to receive the second internal clock signal and another clock signal coupled to or from the clock generator, the false lock detector generating a false lock signal responsive to a predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal, the false lock signal being applied to the second control input of the clock generator to alter the phase of the first internal clock signal.

Claim 14

Dependent Claim 200 words

An internal clock generator circuit, comprising: a clock generator including a locked loop constructed to provide first and second internal clock signals, the first clock signal having a phase determined by first and second phase control signals applied to respective first and second control inputs of the clock generator; a phase detector coupled to the clock generator to receive the first internal clock signal, the phase detector further receiving a reference clock signal, the phase detector being constructed to generate an output signal indicative of the phase of the first internal clock signal relative to the phase of the reference clock signal, the output signal being coupled to the first control input of the clock generator; and a false lock detector coupled to the clock generator to receive the second internal clock signal and another clock signal coupled to or from the clock generator, the false lock detector generating a false lock signal responsive to a predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal, the false lock signal being applied to the second control input of the clock generator to alter the phase of the first internal clock signal.

Claim 15

Dependent Claim 22 words

The internal clock generator circuit of claim 8 wherein the other clock signal comprises a clock signal generated by the locked loop.

Claim 16

Dependent Claim 32 words

The internal clock generator circuit of claim 8 wherein the predetermined relationship between the phase of the second internal clock signal and the phase of the other clock signal comprises 90 degrees.

Claim 17

Dependent Claim 179 words

A delay locked loop, comprising: a delay line receiving a reference clock signal and generating first and second delayed clock signals, the first delayed clock signal having a phase relative to the phase of the reference clock signal that is determined by a signal applied to a control terminal of the delay line; a phase detector coupled to the delay line to receive the first delayed clock signal and coupled to receive the reference clock signal, the phase detector generating a signal at an output terminal indicative of the phase of the first delayed clock signal relative to the phase of the reference clock signal, the output terminal of the phase detector being coupled to the control terminal of the delay line; and a false lock detector coupled to the delay line to receive the second delayed clock signal, the false lock detector being constructed to apply a signal to the control terminal of the delay line responsive to a predetermined characteristic of the second delayed clock signal indicative of a false lock condition of the delay locked loop.

Claim 18

Dependent Claim 179 words

A delay locked loop, comprising: a delay line receiving a reference clock signal and generating first and second delayed clock signals, the first delayed clock signal having a phase relative to the phase of the reference clock signal that is determined by a signal applied to a control terminal of the delay line; a phase detector coupled to the delay line to receive the first delayed clock signal and coupled to receive the reference clock signal, the phase detector generating a signal at an output terminal indicative of the phase of the first delayed clock signal relative to the phase of the reference clock signal, the output terminal of the phase detector being coupled to the control terminal of the delay line; and a false lock detector coupled to the delay line to receive the second delayed clock signal, the false lock detector being constructed to apply a signal to the control terminal of the delay line responsive to a predetermined characteristic of the second delayed clock signal indicative of a false lock condition of the delay locked loop.

Claim 19

Dependent Claim 30 words

The delay locked loop of claim 11 wherein the predetermined characteristic comprises the logic level of the second delayed clock signal at a transition of the first delayed clock signal.

Claim 20

Dependent Claim 31 words

The delay locked loop of claim 11 wherein the predetermined characteristic comprises the phase of the second delayed clock signal relative to the phase of the first delayed delayed clock signal.

Claim 21

Independent Claim 124 words

A method of generating an internal clock signal, comprising: adjusting the phase of the internal clock signal relative to a reference clock signal using a locked loop, the locked loop adjusting the phase of the internal clock signal as a function of the phase relationship between the internal clock signal and the reference clock signal in an attempt to maintain a predetermined phase relationship between the internal clock signal and the reference clock signal; detecting a false lock condition of the locked-loop using at least one clock signal generated by the locked loop and another clock signal coupled to or from the locked loop; and altering the phase of the internal clock signal in a single direction responsive to detecting the false lock condition.

Claim 22

Independent Claim 124 words

A method of generating an internal clock signal, comprising: adjusting the phase of the internal clock signal relative to a reference clock signal using a locked loop, the locked loop adjusting the phase of the internal clock signal as a function of the phase relationship between the internal clock signal and the reference clock signal in an attempt to maintain a predetermined phase relationship between the internal clock signal and the reference clock signal; detecting a false lock condition of the locked-loop using at least one clock signal generated by the locked loop and another clock signal coupled to or from the locked loop; and altering the phase of the internal clock signal in a single direction responsive to detecting the false lock condition.

Claim 23

Dependent Claim 31 words

The method of claim 14 wherein the false lock condition is detected using clock signals from the locked loop having respective phases that differ from each other by approximately 90 degrees.

Claim 24

Dependent Claim 44 words

The method of claim 14 wherein the false lock condition is detected by examining the logic level of the at least one clock signal generated by the locked loop at a transition of the other clock signal coupled to or from the locked loop.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-08-16	2003-02-15	2003-08-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-08-16	2007-02-15	2007-08-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-08-16	2011-02-15	2011-08-17	$7700.00	Window Closed / Lapsed

Synchronous clock generator including a false lock detector

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