EP0704848A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor pipeline memory device eliminating time loss due to difference between pipeline stages from data access
Assignee: NEC Corp
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Filing: 1995-09-26
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Granted: —
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Expires: 2015-09-26
Abstract
Abstract A semiconductor pipeline memory device has a controller (16) for producing first, second and third timing clock signals (PH1/PH2/PH3) for transferring a column address and a read-out data bit through first, second and third pipeline stages (15e/15d; 15f/15g/17g/17h; 17i/17b) to an input-and-output pin (DQ), and long time interval between two of the first, second and third timing clock signals and short time interval between another two of the first, second and third timing clock signals are respectively assigned to one of the first to third pipeline stages with relatively long signal path and another of the first to third pipeline stages with relatively short signal path, thereby decreasing undesirable time loss.
Inventors
- 👤 Yasuji C/O Nec Corporation Koshikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 23:10
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C7/1015; G11C7/1039; G11C7/1072
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
401 words
A semiconductor pipeline memory device comprising: a plurality of addressable memory cells (12; 22) for storing data bits, respectively; a plurality of data propagation paths (BL1 - BLn)) selectively coupled to said plurality of addressable memory cells; an addressing system (14; 24) responsive to an external address signal (ADD) supplied to an address port so as to make said plurality of addressable memory cells selectively accessible; a data propagation system (17; 27) coupled between said plurality of data propagation paths and a data port (DQ); and a pipeline controlling system (16; 26) causing said addressing system and said data propagation system to trace a pipeline sequence from an address input to a data supply, characterized in that said pipeline controlling system (16; 26) produces at least a first timing clock signal (PH1) changed to a first active level in each of pipeline cycles, a second timing clock signal (PH2; PH12) changed to a second active level after said first timing clock signal in said each of said pipeline cycles and a third timing clock signal (PH3; The inverse of PH12) changed to a third active level between said first timing clock signal and said second timing clock signal in said each of said pipeline cycles, said pipeline sequence including a first pipeline stage (15e/15d) close to said address port and having first temporary storage means (15e) responsive to said first timing clock signal (PH1) so as to achieve a first task in a first time interval (t10-t12/ t13-t15) between said first timing clock signal in each of said pipeline cycles and said second timing clock signal in said each of said pipeline cycles, a second pipeline stage (15f/15g/17g/17h) contiguous to said first pipeline stage and having second temporary storage means (15f/17g) responsive to said second and third timing clock signals so as to achieve a second task in a second time interval (t12-t14/ t15-t17) between said second timing clock signal in each of said pipeline cycles and said third timing clock signal in the next pipeline cycle, and a third pipeline stage (17i/17b) contiguous to said second pipeline stage and having third temporary storage means (17i) and responsive to said first timing clock signal so as to achieve a third task in a third time interval (t11-t13/ t14-t16) between said third timing clock signal in each of said pipeline cycles and said first timing clock signal in the next pipeline cycle.
Claim 2
Dependent Claim
222 words
The semiconductor pipeline memory device as set forth in claim 1, in which said addressing system (14; 24) includes a row addressing sub-system (15a) responsive to an external row address sub-signal so as to electrically couple one of groups of said plurality of addressable memory cells (12; 22) to said plurality of data propagation paths (BL1-BLn), and a column addressing sub-system (15b) having an address input circuit (15c) coupled to said address port and producing column address data signals (CL1) from an external column address sub-signal (ADD), first latch circuits (15e) coupled to said address input circuit (15c) and responsive to said first timing clock signal (PH1) so as to temporarily store said column address data signals (CL1), a column address decoder (15d) coupled to said first latch circuits (15e) and producing column address decoded signals (CL2) from said column address data signals (CL1) stored in said first latch circuits (15e), and second latch circuits (15f) coupled to said column address decoder (15d) and responsive to said second timing clock signal (PH2; PH12) so as to temporarily store said column address decoded signals (CL2), said second latch circuits (15f) supplying said column address decoded signals (CL2) to said data propagation system (17; 27) so as to selectively couple said data propagation system (17; 27) to said plurality of data propagation paths (BL1-BLn).
Claim 3
Dependent Claim
352 words
The semiconductor pipeline memory device as set forth in claim 1, in which said addressing system (14; 24) includes a row addressing sub-system (15a) responsive to an external row address sub-signal so as to electrically couple one of groups of said plurality of addressable memory cells (12; 22) to said plurality of data propagation paths (BL1-BLn), and a column addressing sub-system (15b) having an address input circuit (15c) coupled to said address port and producing column address data signals (CL1) from an external column address sub-signal (ADD), first latch circuits (15e) coupled to said address input circuit (15c) and responsive to said first timing clock signal (PH1) so as to temporarily store said column address data signals (CL1), a column address decoder (15d) coupled to said first latch circuits (15e) and producing column address decoded signals (CL2) from said column address data signals (CL1) stored in said first latch circuits (15e), and second latch circuits (15f) coupled to said column address decoder (15d) and responsive to said second timing clock signal (PH2; PH12) so as to temporarily store said column address decoded signals (CL2), said second latch circuits (15f) supplying said column address decoded signals (CL2) to said data propagation system (17; 27) so as to selectively couple said data propagation system (17; 27) to said plurality of data propagation paths (BL1-BLn), said data propagation system (17; 27) including a pipeline write-in data propagation sub-system (17a/17c/17d/17f) coupled to said data port (DQ) for propagating an input data (WD1/WD2/WD3) toward said plurality of data propagation paths (BL1-BLn), a pipeline read-out data propagation sub-system (17g/17h/17i/17b) coupled to said data port (DQ) in parallel to said pipeline write-in data propagation sub-system for propagating an output data (RD1/RD2/RD3) to said data port (DQ), and a column selector (15g) coupled between said plurality of data propagation paths (BL1-BLn) and said pipeline write-in data propagation sub-system and said pipeline read-out data propagation sub-system and responsive to said column address decoded signals (CL2) for selectively coupling said plurality of data propagation paths (BL1-BLn) to one of said pipeline write-i data propagation sub-system and said pipeline read-out data propagation sub-system.
Claim 4
Dependent Claim
39 words
The semiconductor pipeline memory device as set forth in claim 3, in which said data propagation system (17; 27) further includes a plurality of sense amplifier circuits (13; 23) respectively coupled to said plurality of data propagation paths (BL1-BLn).
Claim 5
Dependent Claim
180 words
The semiconductor pipeline memory device as set forth in claim 3, in which said pipeline read-out data propagation sub-system includes a read buffer circuit (17g) coupled to said column selector (15g) and responsive to said third timing clock signal (PH3; The inverse of PH12) so as to temporarily store said output data (RD1), a data amplifier (17h) coupled to said read buffer circuit (17g) for amplifying said output data (RD2), a third latch circuit (17i) coupled to said data amplifier (17h) and responsive to said first timing clock signal (PH1) so as to temporarily store said output data (RD2), and a data output circuit (17b) coupled to said third latch circuit (17i) and producing an output data signal (Sout) from said output data (RD3), said first latch circuits (15e) and said column address decoder (15d) forming said first pipeline stage, said second latch circuits (15f), said column selector (15g), said read buffer circuit (17g) and said data amplifier (17h) forming said second pipeline stage, said third latch circuit (17i) and said data output circuit (17b) forming said third pipeline stage.
Claim 6
Dependent Claim
133 words
The semiconductor pipeline memory device as set forth in claim 3, in which said pipeline write-in data propagation sub-system has a data input circuit (17a) coupled to said data port (DQ) and producing said input data (WD1) from an input data signal (Sin), a third latch circuit (17c) coupled to said data input circuit (17a) and responsive to said first timing clock signal (PH1) so as to temporarily store said input data (WD1), a fourth latch circuit (17d) coupled to said third latch circuit (17c) and responsive to said second timing clock signal (PH2; PH12) so as to temporarily store said input data (WD1), and a write buffer circuit (17f) coupled between said fourth latch circuit (17d) and said column selector (15g) for transferring said input data (WD3) to said column selector (15g).
Claim 7
Dependent Claim
91 words
The semiconductor pipeline memory device as set forth in claim 1, in which said pipeline controlling system (16; 26) includes a clock input circuit (16a) supplied with an external clock signal (CLK) for producing said first timing clock signal (PH1), and a delay circuit (16b; 26b/26g) introducing a first time delay into said first timing clock signal (PH1) for producing said second timing clock (PH2; PH12) signal and a second time delay into said first timing clock signal (PH1) for producing said third timing clock signal (PH3; the inverse of PH12).
Claim 8
Dependent Claim
29 words
The semiconductor pipeline memory device as set forth in claim 7, in which said first active level is identical with said second active level and said third active level.
Claim 9
Dependent Claim
69 words
The semiconductor pipeline memory device as set forth in claim 7, in which said delay circuit (16b) includes a first delay sub-circuit (16c) introducing said first time delay into said first timing clock signal (PH1) for producing said second timing clock signal (PH2), and a second delay sub-circuit (16d) introducing said second time delay into said first timing clock signal (PH1) for producing said third timing clock signal (PH3).
Claim 10
Dependent Claim
110 words
The semiconductor pipeline memory device as set forth in claim 7, in which said delay circuit includes a first delay sub-circuit (26c) coupled to said clock input circuit (16a), a first inverter (26e) coupled to said clock input circuit (16a), a second delay sub-circuit (26d) coupled to said first inverter (26e), an OR gate (26f) coupled to an output node of said first delay sub-circuit (26c) and an output node of said second delay sub-circuit (26d) and producing said second timing clock signal (PH12), and a second inverter (26g) coupled to an output node of said OR gate (26f) for producing said third timing clock signal (the inverse of PH12).
Claim 11
Dependent Claim
172 words
The semiconductor pipeline memory device as set forth in claim 7, in which said first time delay is equal to a first time consumed by a signal propagation through said first pipeline stage, and said second time delay satisfies following equations t1 + t21 = (t1 + t2)/2 + t D 2 t22 = (t1 + t2)/2 - t D 2 where t1 is said first time, t2 is a second time consumed by a signal propagation through said second pipeline stage, t21 is a third time consumed by a signal propagation from a first sub-means (15f) of said second temporary storage means responsive to said second timing clock signal (PH2; PH12) to a second sub-means (17f) of said second temporary storage means responsive to said third timing clock signal (PH3; the inverse of PH12), t D 2 is said second time delay and t22 is a fourth time consumed by a signal propagation from said second sub-means to said third temporary storage means (17i) responsive to said first timing clock signal.
References Cited (Backward Citations)
JPS61148692A
Cited
JPH0676566A
Cited
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