US5933032A — Apparatus and method for generating a pulse signal

Claim 1

Independent Claim 119 words

A circuit for generating a pulse signal comprising: a first circuit configured to generate a first state of the pulse signal in response to a transition of an input signal at a first input from a first state to a second state; and a second circuit coupled to a second input of the first circuit, the second circuit configured to delay the pulse signal to the second input of the first circuit for a first programmable amount of time, said first circuit configured to generate the first state of the pulse signal for at least a second programmable amount of time when the input signal remains in said second state for at least the first programmable amount of time.

Claim 2

Dependent Claim 119 words

A circuit for generating a pulse signal comprising: a first circuit configured to generate a first state of the pulse signal in response to a transition of an input signal at a first input from a first state to a second state; and a second circuit coupled to a second input of the first circuit, the second circuit configured to delay the pulse signal to the second input of the first circuit for a first programmable amount of time, said first circuit configured to generate the first state of the pulse signal for at least a second programmable amount of time when the input signal remains in said second state for at least the first programmable amount of time.

Claim 3

Dependent Claim 90 words

The circuit of claim 1, wherein the first circuit comprises: a first logic device generating a first intermediate signal in response to said input signal; a programmable delay device coupled to said first logic device so as to receive said first intermediate signal and to produce a second intermediate signal the second programmable amount of time after receiving said first intermediate signal; and a logic circuit coupled to the programmable delay device, said logic circuit outputting the pulse signal responsive to said first intermediate signal and said second intermediate signal.

Claim 4

Dependent Claim 56 words

A circuit as in claim 2 wherein the programmable delay device includes: a plurality of signal transmission paths each having a different propagation delay; and a programmable element coupled to the plurality of signal transmission paths and programmed to select one of the plurality of signal transmission paths to generate the second programmable amount of time.

Claim 5

Dependent Claim 14 words

A circuit as in claim 3 wherein said programmable element is a programmable fuse.

Claim 6

Dependent Claim 59 words

A circuit as in claim 4 wherein a first one of the transmission paths is selected when said programmable fuse is blown, and a second one of the transmission paths is selected when said programmable fuse is not blown, wherein the propagation delay of the first transmission path is longer than the propagation delay of the second transmission path.

Claim 7

Dependent Claim 24 words

The circuit of claim 1, wherein said second state of the pulse signal has a minimum duration of the first programmable amount of time.

Claim 8

Dependent Claim 25 words

The circuit of claim 1, wherein the second circuit prevents the first circuit from generating another pulse signal during the first programmable amount of time.

Claim 9

Dependent Claim 63 words

A circuit as in claim 2 wherein the logic circuit comprises: a second logic device coupled to said programmable delay device and generating a third intermediate signal responsive to said second intermediate signal; and a third logic device coupled to the first and second logic devices, the third logic device outputting the pulse signal in response to the first and third intermediate signals.

Claim 10

Dependent Claim 15 words

A circuit as in claim 8 wherein said second logic device receives a reset signal.

Claim 11

Dependent Claim 31 words

The circuit of claim 2, wherein the programmable delay device comprises: a first programmable delay circuit; and a second programmable delay circuit coupled in series with the first programmable delay circuit.

Claim 12

Dependent Claim 28 words

The circuit of claim 10, wherein the first programmable delay circuit has a first programmable delay different than a second programmable delay of the second programmable delay circuit.

Claim 13

Dependent Claim 14 words

The circuit of claim 1, wherein the second circuit comprises a programmable delay device.

Claim 14

Dependent Claim 48 words

A circuit as in claim 12 wherein the programmable delay device includes: a plurality of signal transmission paths each having a different propagation delay; and a programmable element coupled to the plurality of signal transmission paths and programmed to select one of the plurality of signal transmission paths.

Claim 15

Dependent Claim 14 words

A circuit as in claim 13 wherein said programmable element is a programmable fuse.

Claim 16

Dependent Claim 59 words

A circuit as in claim 14 wherein a first one of the transmission paths is selected when said programmable fuse is blown, and a second one of the transmission paths is selected when said programmable fuse is not blown, wherein the propagation delay of the first transmission path is shorter than the propagation delay of the second transmission path.

Claim 17

Independent Claim 106 words

A method of generating a pulse signal comprising the steps of: generating, from a circuit, a first state of the pulse signal in response to a transition of an input signal from a first state to a second state, said input signal received at a first input of said circuit; and providing the pulse signal to a second input of the circuit after a first programmable amount of delay time, said pulse signal remaining in said first state for at least a second programmable amount of time when the input signal remains in said second state for at least the first programmable amount of delay time.

Claim 18

Independent Claim 106 words

A method of generating a pulse signal comprising the steps of: generating, from a circuit, a first state of the pulse signal in response to a transition of an input signal from a first state to a second state, said input signal received at a first input of said circuit; and providing the pulse signal to a second input of the circuit after a first programmable amount of delay time, said pulse signal remaining in said first state for at least a second programmable amount of time when the input signal remains in said second state for at least the first programmable amount of delay time.

Claim 19

Dependent Claim 28 words

The method of claim 16, further comprising the step of generating a second state of the pulse signal for at least the first programmable amount of delay time.

Claim 20

Dependent Claim 116 words

A pulse signal generator, comprising: a first circuit configured to generate a first state of a pulse signal in response to a transition of an input signal at a first input from a first state to a second state, the pulse signal having a first state for at least a first predetermined amount of time when the input signal remains in said second state for at least a second predetermined amount of time; and a second circuit configured to delay the pulse signal to a second input of the first circuit for the second predetermined amount of time, such that said pulse signal has said first state for at least said second predetermined amount of time.

Claim 21

Dependent Claim 116 words

A pulse signal generator, comprising: a first circuit configured to generate a first state of a pulse signal in response to a transition of an input signal at a first input from a first state to a second state, the pulse signal having a first state for at least a first predetermined amount of time when the input signal remains in said second state for at least a second predetermined amount of time; and a second circuit configured to delay the pulse signal to a second input of the first circuit for the second predetermined amount of time, such that said pulse signal has said first state for at least said second predetermined amount of time.

Claim 22

Dependent Claim 14 words

The circuit of claim 18, wherein the second predetermined amount of time is programmable.

Claim 23

Dependent Claim 14 words

The circuit of claim 18, wherein the first predetermined amount of time is programmable.

Claim 24

Dependent Claim 92 words

The circuit of claim 18, wherein the first circuit comprises: a first logic circuit generating a first intermediate signal in response to said input signal; a programmable delay device coupled to said first logic circuit so as to receive said first intermediate signal and to generate a second intermediate signal the first predetermined amount of time after receiving said first intermediate signal; and a second logic circuit coupled to the programmable delay device, said second logic circuit outputting the pulse signal responsive to said first intermediate signal and said second intermediate signal.

Claim 25

Dependent Claim 56 words

A circuit as in claim 21, wherein the programmable delay device includes: a plurality of signal transmission paths each having a different propagation delay; and a programmable element coupled to the plurality of signal transmission paths and programmed to select one of the plurality of signal transmission paths to generate the first predetermined amount of time.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2002-08-02	2003-02-01	2003-08-03	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2006-08-02	2007-02-01	2007-08-03	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2010-08-02	2011-02-01	2011-08-03	$7700.00	Window Closed / Lapsed

Apparatus and method for generating a pulse signal

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