US5926034A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fuse option for multiple logic families on the same die
Assignee: Round Rock Research LLC
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Filing: 1997-08-14
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Granted: 1999-07-20
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Expires: 2017-08-14
Abstract
Abstract A chip's interface is selected by using a fuse option coupled between integrated circuitry on the chip and logic circuitry. Fuse options correspond to antifuses or fuses. In one embodiment, a plurality of fuse options are manufactured in an integrated circuit such that a fuse option is coupled between integrated circuitry on the chip and separate and complete logic circuitry for different logic types used to interface a chip. In another embodiment, only one type of logic circuitry is manufactured on a chip, such that the logic circuitry has both a pull-up and pull-down transistor. A fuse is coupled with a pull-up control circuit of the logic circuitry. When the fuse is blown, the output circuit corresponds to GTL-terminated logic circuitry, using only the pull-down transistor. In a further embodiment, an antifuse is coupled with the pull-up control circuit. When the antifuse is programmed, default GTL-terminated logic is converted to TTL family output logic, or another logic which uses both pull-up and pull-down transistors in its logic circuitry.
Inventors
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
61 words
A chip interface for a semiconductor chip, comprising: at least two logic circuits of mutually different families formed on the semiconductor chip and both coupled to the same input connection and to the same output connection; and at least two fuses, wherein each fuse is operatively coupled to one of the logic circuits to enable only one of the logic circuits.
Claim 2
Dependent Claim
61 words
A chip interface for a semiconductor chip, comprising: at least two logic circuits of mutually different families formed on the semiconductor chip and both coupled to the same input connection and to the same output connection; and at least two fuses, wherein each fuse is operatively coupled to one of the logic circuits to enable only one of the logic circuits.
Claim 3
Dependent Claim
59 words
The chip interface of claim 1, wherein each logic circuit is selected from the group consisting of: a transistor--transistor logic circuit, a low voltage transistor--transistor logic circuit, a gunning transceiver logic-unterminated circuit, a gunning transceiver logic-terminated circuit, a gunning transceiver logic-unterminated circuit, a high speed transceiver logic-terminated circuit, a small swing transistor logic circuit, and a center-tapped-terminated logic circuit.
Claim 4
Dependent Claim
29 words
The chip interface of claim 1, wherein only one fuse is unblown such that integrated circuitry on the semiconductor chip is electrically-coupled with only one of the logic circuits.
Claim 5
Dependent Claim
12 words
The chip interface of claim 3, wherein the fuses are laser fuses.
Claim 6
Dependent Claim
61 words
A chip interface for a semiconductor chip, comprising: at least two logic circuits of mutually different families formed on the semiconductor chip and both coupled to the same input connection and to the same output connection; and at least two antifuses, wherein each antifuse is operatively coupled to one of the logic circuits to enable only one of the logic circuits.
Claim 7
Dependent Claim
61 words
A chip interface for a semiconductor chip, comprising: at least two logic circuits of mutually different families formed on the semiconductor chip and both coupled to the same input connection and to the same output connection; and at least two antifuses, wherein each antifuse is operatively coupled to one of the logic circuits to enable only one of the logic circuits.
Claim 8
Dependent Claim
49 words
The chip interface of claim 5, wherein each logic circuit is selected from the group consisting of: a transistor--transistor logic circuit, a low voltage transistor--transistor logic circuit, a gunning transceiver logic-unterminated circuit, a high speed transceiver logic-terminated circuit, a small swing transistor logic circuit, and a center-tapped-terminated logic circuit.
Claim 9
Dependent Claim
29 words
The chip interface of claim 5, wherein only one antifuse is programmed such that integrated circuitry on the semiconductor chip is electrically-coupled with only one of the logic circuits.
Claim 10
Independent Claim
95 words
A method for selecting a logic family for a chip interface, comprising: providing a semiconductor chip with at least two logic circuits of mutually different families coupled in parallel between an input signal connection and an output signal connection of integrated circuitry on the semiconductor chip, wherein the semiconductor chip has at least two fuses, respectively coupled between the integrated circuitry and each logic circuit; and programming the fuses to connect one of the logic circuits between the input connection and the output connection, and to disconnect at least one other of the logic circuits.
Claim 11
Independent Claim
95 words
A method for selecting a logic family for a chip interface, comprising: providing a semiconductor chip with at least two logic circuits of mutually different families coupled in parallel between an input signal connection and an output signal connection of integrated circuitry on the semiconductor chip, wherein the semiconductor chip has at least two fuses, respectively coupled between the integrated circuitry and each logic circuit; and programming the fuses to connect one of the logic circuits between the input connection and the output connection, and to disconnect at least one other of the logic circuits.
Claim 12
Dependent Claim
53 words
The method of claim 8, wherein the logic circuits are selected from the group consisting of: a transistor--transistor logic circuit, a low voltage transistor--transistor logic circuit, a gunning transceiver logic-unterminated circuit, a gunning transceiver logic-terminated circuit, a high speed transceiver logic-terminated circuit, a small swing transistor logic circuit and a center-tapped-terminated logic circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |