Integrated circuit having multiple data outputs sharing a resistor network

Claim 2

In an integrated circuit having multiple output terminals, an output driver circuit comprising: a plurality of output drivers, each comprising: a drive transistor, having a conduction path between an associated output terminal and a bias voltage, and having a control terminal; and a logic circuit, having an output coupled to the control terminal of said drive transistor, and having an input for receiving a data input signal to be presented at said associated output terminal, said logic circuit having first and second bias nodes; wherein the first bias nodes of each of said logic circuits are connected together; and further comprising: a first resistor network coupled between said first bias nodes of said logic circuits and a first bias voltage terminal.

Claim 3

The circuit of claim 1, wherein said first resistor network comprises: a first resistor.

Claim 4

The circuit of claim 2, wherein said first resistor network further comprises: a second resistor connected in parallel with said first resistor.

Claim 5

The circuit of claim 2, wherein said first resistor network further comprises: a second resistor connected in series with said first resistor.

Claim 6

The circuit of claim 4, wherein said first resistor network further comprises: a first conductor connected in parallel with said first resistor.

Claim 7

The circuit of claim 5, wherein said first conductor comprises a first fuse.

Claim 8

The circuit of claim 5, wherein said first conductor comprises a first shorting transistor having its conduction path connected in parallel with said first resistor, and having a control terminal; and further comprising: a first fuse connected between a fuse bias voltage and a first node; a first logic circuit having an input connected to said first node, and having an output connected to the control terminal of said first shorting transistor, said first logic circuit for presenting a voltage at said control terminal to turn off said first shorting transistor responsive to said first fuse being closed, and for presenting a voltage at said control terminal to turn on said first shorting transistor responsive to said first fuse being open.

Claim 9

The circuit of claim 5, further comprising: a second conductor connected in parallel with said second resistor.

Claim 10

The circuit of claim 6, further comprising a second fuse connected in parallel with said second resistor.

Claim 11

The circuit of claim 7, further comprising a second shorting transistor having its conduction path connected in parallel with said second resistor, and having a control terminal; and further comprising: a second fuse connected between said fuse bias voltage and a second node; a second logic circuit having an input connected to said second node, and having an output connected to the control terminal of said second shorting transistor, said second logic circuit for presenting a voltage at said control terminal to turn off said second shorting transistor responsive to said second fuse being closed, and for presenting a voltage at said control terminal to turn on said second shorting transistor responsive to said second fuse being open.

Claim 12

The circuit of claim 1, wherein the second bias nodes of each of said logic circuits are connected together; and further comprising: a second resistor network coupled between said second bias nodes of said logic circuit and a second bias voltage terminal.

Claim 13

The circuit of claim 1, wherein each of said logic circuits also have an input for receiving a disable signal; and wherein each of said logic circuits present, at the control terminal of its associated drive transistor, a voltage to turn off said drive transistor responsive to said disable signal indicating that said output drivers are to be disabled.

Claim 14

An integrated circuit having multiple output terminals, comprising: a plurality of output terminals; a plurality of output driver circuits, each associated with an output terminal, and each comprising: a pull-up transistor having its source/drain path connected between a bias voltage and its associated output terminal, and having a control terminal; a pull-down transistor having its source/drain path connected between a reference voltage and its associated output terminal, and having a control terminal; a first logic circuit having an input for receiving an input data signal, having a bias node and having a reference node, and having an output coupled to said control terminal of said pull-up transistor; and a second logic circuit having an input for receiving said input data signal, having a bias node and having a reference node, and having an output coupled to said control terminal of said pull-down transistor; a first resistor network coupled between said bias nodes of said first logic circuits of said plurality of output driver circuits and said bias voltage; a second resistor network coupled between said reference nodes of said first logic circuits of said plurality of output driver circuits and said reference voltage; a third resistor network coupled between said bias nodes of said second logic circuits of said plurality of output driver circuits and said bias voltage; and a fourth resistor network coupled between said reference nodes of said second logic circuits of said plurality of output driver circuits and said reference voltage.

Claim 15

An integrated circuit having multiple output terminals, comprising: a plurality of output terminals; a plurality of output driver circuits, each associated with an output terminal, and each comprising: a pull-up transistor having its source/drain path connected between a bias voltage and its associated output terminal, and having a control terminal; a pull-down transistor having its source/drain path connected between a reference voltage and its associated output terminal, and having a control terminal; a first logic circuit having an input for receiving an input data signal, having a bias node and having a reference node, and having an output coupled to said control terminal of said pull-up transistor; and a second logic circuit having an input for receiving said input data signal, having a bias node and having a reference node, and having an output coupled to said control terminal of said pull-down transistor; a first resistor network coupled between said bias nodes of said first logic circuits of said plurality of output driver circuits and said bias voltage; a second resistor network coupled between said reference nodes of said first logic circuits of said plurality of output driver circuits and said reference voltage; a third resistor network coupled between said bias nodes of said second logic circuits of said plurality of output driver circuits and said bias voltage; and a fourth resistor network coupled between said reference nodes of said second logic circuits of said plurality of output driver circuits and said reference voltage.

Claim 16

The integrated circuit of claim 13, wherein each of said resistor networks comprises: a first resistor.

Claim 17

The integrated circuit of claim 14, wherein each of said resistor networks further comprises: a second resistor connected in parallel with said first resistor.

Claim 18

The integrated circuit of claim 14, wherein each of said resistor networks further comprises: a second resistor connected in series with said first resistor.

Claim 19

The circuit of claim 16, wherein each of said resistor networks further comprises: a conductor connected in parallel with said first resistor.

Claim 20

The circuit of claim 17, wherein said conductor comprises a fuse.

Claim 21

The circuit of claim 18, wherein said conductor comprises a shorting transistor having its conduction path connected in parallel with said first resistor, and having a control terminal; and further comprising: a fuse connected between a fuse bias voltage and a node; a logic circuit having an input connected to said node, and having an output connected to the control terminal of said shorting transistor, said logic circuit for presenting a voltage at said control terminal to turn off said shorting transistor responsive to said fuse being closed, and for presenting a voltage at said control terminal to turn on said shorting transistor responsive to said fuse being open.

Claim 24

The method of claim 20, wherein said first resistor network comprises a plurality of resistors in series, each having a fuse connected in parallel therewith; and wherein said adjusting step comprises: opening one of said fuses in said first resistor network.

Claim 25

The method of claim 20, wherein said first resistor network comprises a plurality of resistors in series, each having a fuse circuit connected in parallel therewith, said fuse circuit arranged so that, with said fuse intact, the parallel resistor is not shorted out; and wherein said adjusting step comprises: opening one of said fuses to short out the resistor connected in parallel with the fuse circuit in which the fuse is opened.

Claim 26

The method of claim 20, further comprising: measuring a parameter of said circuit which is indicative of the switching speed of said circuit; and wherein said adjusting step is performed responsive to the result of said measuring step.

Claim 27

An output driver circuit, comprising: a drive transistor having a conduction path between an output terminal and a bias voltage, and having a control terminal; a logic circuit having an output coupled to the control terminal of said drive transistor and having an input for receiving a data input signal to be presented at said associated output terminal; a first resistor network connected between a bias node of said logic circuit and a bias voltage node, comprising: a plurality of resistors connected in series between said bias voltage node and said bias node; a plurality of conductors, each connected in parallel with one of said plurality of resistors, for allowing selection of the resistance of said first resistor network.

Claim 28

An output driver circuit, comprising: a drive transistor having a conduction path between an output terminal and a bias voltage, and having a control terminal; a logic circuit having an output coupled to the control terminal of said drive transistor and having an input for receiving a data input signal to be presented at said associated output terminal; a first resistor network connected between a bias node of said logic circuit and a bias voltage node, comprising: a plurality of resistors connected in series between said bias voltage node and said bias node; a plurality of conductors, each connected in parallel with one of said plurality of resistors, for allowing selection of the resistance of said first resistor network.

Claim 29

The output driver of claim 24, wherein each of said plurality of conductors comprises a fuse.

Claim 30

The output driver of claim 24, wherein each of said plurality of conductors comprises a shorting transistor having its conduction path connected in parallel with its associated parallel resistor, and each having a control terminal; and further comprising: a plurality of fuse circuits, each associated with a resistor, and each comprising: a fuse; and a logic circuit having an output coupled to the control terminal of an associated shorting transistor, said logic circuit for controlling said shorting transistor to be off responsive to said fuse being closed, and to be on responsive to said fuse being open.

Claim 31

The output driver of claim 24, further comprising: a second resistor network connected between a reference node of said logic circuit and a reference voltage node, comprising: a plurality of resistors connected in series between said bias voltage node and said bias node; a plurality of conductors, each connected in parallel with one of said plurality of resistors, for allowing selection of the resistance of said first resistor network.

Claim 32

The output driver of claim 27, wherein each of said plurality of conductors comprises a fuse.

Claim 33

The output driver of claim 27, wherein each of said plurality of conductors comprises a shorting transistor having its conduction path connected in parallel with its associated parallel resistor, and each having a control terminal; and further comprising: a plurality of fuse circuits, each associated with a resistor, and each comprising: a fuse; and a logic circuit having an output coupled to the control terminal of an associated shorting transistor, said logic circuit for controlling said shorting transistor to be off responsive to said fuse being closed, and to be on responsive to said fuse being open.