Multiple output field effect transistor logic

Claim 1

An integrated circuit including at least one multiple output logic gate, with said logic gate comprising: a string of single drain field-effect transistors (e.g. T31, T32, T35, T36) connected between a load transistor that is coupled to, a higher power supply voltage level (e.g. V DD ) and a lower power supply voltage level (e.g. V SS ), wherein said transistors pull a given output node located between said load transistor and the top of said string toward said lower voltage level in response to logical input signals applied to the gates of said transistors; and at least one additional output node (e.g. 33) connected to an intermediate point of said string that is lower than said given output node. characterized in that said logic gate further comprises at least one addition transistor (e.g. T34) connected, in parallel with one or more of the transistors in said string, whereby a false discharge path exists; and wherein the logic input of one of said transistors in said string (e.g. T31) that is coupled between said higher voltage level and said additional output node is always mutually exclusive to the input of said additional transistor, whereby one of said transistors and said additional transistor is always turned off, thereby preventing a discharge of said additional output node through said false discharge path.