Dynamic MOS-logic in interlace-techniques

Claim 1

An integrated digital circuit arrangement with MOS field-effect transistors, which arrangement comprises a combinatorial circuit for applying a logic operation to a plurality of input signals, which combinatorial circuit comprises a plurality of branches, there being provided means for applying said input signals as well as an output, which is coupled to a first node of the arrangement, whose potential at a specific instant is representative of the result of the logic operation and depends on whether the capacitance of the first node is charged or not, characterized in that: each branch is provided with a pre-charging transistor while for isolating the individual branches from each other there is provided a transistor arranged as a transfer gate for each branch, whose gate-electrode is connected to the relevant branch, the source and drain electrodes of said transistors arranged as a transfer gate being included in series between a common reference point and the first node, wherein the charging time of said first node capacitance is essentially independent of the number of transistors in said transfer gate and said charging time occurs prior to said specific instant.