US4942309A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High side driver MOS circuit
Assignee: STMicroelectronics SRL
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Filing: 1989-02-22
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Granted: 1990-07-17
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Expires: 2009-02-22
Abstract
Abstract A MOS high side driver circuit switching a supply voltage by means of a power switching transistor M1 driven by a driving circuit in function of a drive switching signal C, utilizes a flip-flop for driving the gate of the power switching transistor M1. The inputs SET and RESET of the flip-flop are respectively connected to the drain node of two, grounded source, input transistors supplied from a V GG rail maintained at a constant potential difference from the source (output) node of the power switching transistor M1. Two pulse signals C R , C S and corresponding to a rising and to a falling edge of the drive switching signal C from which they are derived by suitable circuit means, are respectively applied to the gates of the two input transistors. The driving circuit dissipates only during transitions in contrast to the driving circuits of the prior art.
Inventors
- 👤 Davide Chieli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:45
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/06; H03K17/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
359 words
A high side driver circuit for switching a supply voltage V DD across a load Zc by means of a power switching transistor M1, which has a drain connected to the supply voltage rail V DD , and a source connected to a terminal of the load, the other terminal of the load being connected to the ground, with said power switching transistor being driven by a driving circuit controlled by a drive switching signal C, said circuit comprising; an input circuit means having an input terminal to which said drive switching signal C is applied, said input circuit means producing at two output terminals thereof, a first pulse signal C S which is a positive pulse coinciding with a falling edge of said switching signal C and a second pulse signal C R which is a positive pulse coinciding with a rising edge of said switching signal C, respectively; a first transistor M2S having a grounded source and being driven by said first signal C S , said first transistor having a drain connected through a load element capable of maintaining the said potential of said transistor at a stationary logic 1 level, when said transistor is turned OFF from a supply node V GG of the circuit; a second transistor M2R having a grounded source and being driven by said second pulse signal C R and having a drain connected through a load element capable of maintaining the drain potential of said transistor at a stationary logic 1 level when said transistor is turned OFF from said supply node V GG of the circuit; a SET-RESET type flip-flop having a SET input terminal connected to the drain of said first transistor M2S and a RESET input terminal connected to the drain of said second transistor M2R and having an output terminal connected to the gate of said power switching transistor M1; wherein a constant potential difference is being maintained between said supply node V GG of the circuit and the source of said power switching transistor M1 by means of a voltage generator, and wherein said driving circuit dissipates only during transitions from one state to another.
Claim 2
Dependent Claim
359 words
A high side driver circuit for switching a supply voltage V DD across a load Zc by means of a power switching transistor M1, which has a drain connected to the supply voltage rail V DD , and a source connected to a terminal of the load, the other terminal of the load being connected to the ground, with said power switching transistor being driven by a driving circuit controlled by a drive switching signal C, said circuit comprising; an input circuit means having an input terminal to which said drive switching signal C is applied, said input circuit means producing at two output terminals thereof, a first pulse signal C S which is a positive pulse coinciding with a falling edge of said switching signal C and a second pulse signal C R which is a positive pulse coinciding with a rising edge of said switching signal C, respectively; a first transistor M2S having a grounded source and being driven by said first signal C S , said first transistor having a drain connected through a load element capable of maintaining the said potential of said transistor at a stationary logic 1 level, when said transistor is turned OFF from a supply node V GG of the circuit; a second transistor M2R having a grounded source and being driven by said second pulse signal C R and having a drain connected through a load element capable of maintaining the drain potential of said transistor at a stationary logic 1 level when said transistor is turned OFF from said supply node V GG of the circuit; a SET-RESET type flip-flop having a SET input terminal connected to the drain of said first transistor M2S and a RESET input terminal connected to the drain of said second transistor M2R and having an output terminal connected to the gate of said power switching transistor M1; wherein a constant potential difference is being maintained between said supply node V GG of the circuit and the source of said power switching transistor M1 by means of a voltage generator, and wherein said driving circuit dissipates only during transitions from one state to another.
Claim 3
Dependent Claim
97 words
The circuit according to claim 1, wherein said input circuit means comprise a logic NOT gate, a logic AND gate and a logic NOR gate; said drive switching signal C being applied to an input of each of said logic gates, the output signal C of said NOT gate having a certain delay with respect to the input switching signal C and being applied to a second input of each of said other logic AND and NOR gates, thus obtaining at the respective output terminals of said gates two pulse signals C R and C S .
Claim 4
Dependent Claim
19 words
The circuit according to claim 1, wherein said load of each the transistors M2S and M2R is a resistor.
Claim 5
Dependent Claim
20 words
The circuit according to claim 1, wherein said load of each the transistors M2S and M2R is a current generator.
Claim 6
Dependent Claim
34 words
The circuit according to claim 1, wherein a limiting diode is connected between the source of the power switching transistor M1 and the drain of each of said two transistors M2S and M2R, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-16 | 1994-01-15 | 1994-07-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-16 | 1998-01-15 | 1998-07-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-16 | 2002-01-15 | 2002-07-17 | $7700.00 | Window Closed / Lapsed |