US5373199A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS transistor output circuit
Assignee: Mitsubishi Electric Corp
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Filing: 1992-12-17
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Granted: 1994-12-13
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Expires: 2012-12-17
Abstract
Abstract A transistor (2P) permitted to select whether to operate as a common-source circuit or as a source follower type circuit is connected in series with a transistor (1P) operating as a common-source circuit. This selection is achieved by the control of a switching circuit (SP). Selection is permitted to be made whether to oscillate the amplitude of an output potential over the full range or to limit the amplitude by the amount of a threshold level of the transistor. An MOS transistor output circuit is provided which limits or unlimits the amplitude of the output potential for reducing undesired radiation, malfunctions due to noises and heat generated and for high-speed operation of logic circuits. (FIG. 1)
Inventors
- 👤 Daisuke Shichinohe
- 👤 Kenji Nakao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/003; H03K19/00315; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
127 words
A MOS transistor output circuit, comprising: an input terminal receiving an input signal; an output terminal; first and second potential points; first switching means having a first terminal connected to said second potential point, a second terminal, and a common terminal; a first MOS transistor of a first conductivity type having a control electrode connected to said input terminal, and first and second current electrodes; and a second MOS transistor of the first conductivity type having a control electrode connected to said common terminal of said first switching means, a first current electrode, and a second current electrode connected to said second terminal of said first switching means, said first and second MOS transistors being connected in series between said first potential point and said output terminal.
Claim 2
Dependent Claim
127 words
A MOS transistor output circuit, comprising: an input terminal receiving an input signal; an output terminal; first and second potential points; first switching means having a first terminal connected to said second potential point, a second terminal, and a common terminal; a first MOS transistor of a first conductivity type having a control electrode connected to said input terminal, and first and second current electrodes; and a second MOS transistor of the first conductivity type having a control electrode connected to said common terminal of said first switching means, a first current electrode, and a second current electrode connected to said second terminal of said first switching means, said first and second MOS transistors being connected in series between said first potential point and said output terminal.
Claim 3
Dependent Claim
63 words
The MOS transistor output circuit of claim 1, wherein said first current electrode of the first MOS transistor is connected to said second current electrode of said second MOS transistor, and said second current electrode of said first MOS transistor is connected to said output terminal, and said first current electrode of said second MOS transistor is connected to said first potential point.
Claim 4
Dependent Claim
63 words
The MOS transistor output circuit of claim 1, wherein said first current electrode of said first MOS transistor is connected to said first potential point, and said second current electrode of said first MOS transistor is connected to said first current electrode of said second MOS transistor, and said second current electrode of said second MOS transistor is connected to said output terminal.
Claim 5
Dependent Claim
22 words
The MOS transistor output circuit of claim 1, wherein said first switching means includes a plurality of wires made of aluminum alloy.
Claim 6
Dependent Claim
82 words
The MOS transistor output circuit of claim 4, wherein said wires include a first wire corresponding to said common terminal of said first switching means, and second and third wires corresponding to said first and second terminals of said first switching means, respectively, and formed in a layer different from a layer in which said first wire is formed, and said first switching means further includes a through hole for connecting one of said second and third wires to said first wire.
Claim 7
Dependent Claim
44 words
The MOS transistor output circuit of claim 1, further comprising: a third MOS transistor of a second conductivity type having a control electrode connected to said input terminal, and first and second current electrodes connected between said output terminal and said second potential point.
Claim 8
Dependent Claim
41 words
The MOS transistor output circuit of claim 6, wherein said first current electrode of said third MOS transistor is connected to said second potential point, and said second current electrode of said third MOS transistor is connected to said output terminal.
Claim 9
Dependent Claim
92 words
The MOS transistor output circuit of claim 6, further comprising: second switching means having a first terminal connected to said first potential point, a second terminal, and a common terminal; and a fourth MOS transistor of the second conductivity type having a control electrode connected to said common terminal of said second switching means, a first current electrode, and a second current electrode connected to said second terminal of said second switching means, said third and fourth MOS transistors being connected in series between said second potential point and said output terminal.
Claim 10
Dependent Claim
63 words
The MOS transistor output circuit of claim 8, wherein said first current electrode of said third MOS transistor is connected to said second current electrode of said fourth MOS transistor, and said second current electrode of said third MOS transistor is connected to said output terminal, and said first current electrode of said fourth MOS transistor is connected to said second potential point.
Claim 11
Dependent Claim
139 words
The MOS transistor output circuit of claim 1, wherein said first switching means includes a control terminal receiving a switching signal determining whether to connect said common terminal of said first switching means to said first or second terminal of said first switching means, a third MOS transistor of a second conductivity type having a first current electrode connected to said first terminal of said first switching means, a second current electrode connected to said common terminal of said first switching means, and a control electrode connected to said control terminal, and a fourth MOS transistor of the first conductivity type having a first current electrode connected to said second terminal of said first switching means, a second current electrode connected to said common terminal of said first switching means, and a control electrode connected to said control terminal.
Claim 12
Dependent Claim
139 words
The MOS transistor output circuit of claim 8, wherein said first switching means includes a control terminal receiving a switching signal determining whether to connect said common terminal of said first switching means to said first or second terminal of said first switching means, a fifth MOS transistor of the second conductivity type having a first current electrode connected to said first terminal of said first switching means, a second current electrode connected to said common terminal of said first switching means, and a control electrode connected to said control terminal, and a sixth MOS transistor of the first conductivity type having a first current electrode connected to said second terminal of said first switching means, a second current electrode connected to said common terminal of said first switching means, and a control electrode connected to said control terminal.
Claim 13
Dependent Claim
104 words
The MOS transistor output circuit of claim 6, further comprising: a fourth MOS transistor of the second conductivity type having first and second current electrodes connected to said second and first current electrodes of said first MOS transistor, respectively, and a control electrode; and a fifth MOS transistor of the first conductivity type having first and second current electrodes connected to said second and first current electrodes of said third MOS transistor, respectively, and a control electrode connected to said control electrode of said fourth MOS transistor, said control electrode of said fifth MOS transistor receiving a logically inverted signal of said input signal.
Claim 14
Dependent Claim
35 words
The MOS transistor output circuit of claim 12, further comprising: an inverter having an input end connected to said input terminal and an output end connected to said control electrode of said fifth MOS transistor.
Claim 15
Dependent Claim
104 words
A MOS transistor output circuit, comprising: an input terminal; an output terminal; a first potential point; a first MOS transistor of a first conductivity type having a control electrode connected to said input terminal, and first and second current electrodes; a second MOS transistor of the first conductivity type having a control electrode, a first current electrode, and a second current electrode connected to said control electrode thereof; and a first switch connected between said first and second current electrodes of said second MOS transistor, said first and second MOS transistors being connected in series between said first potential point and said output terminal.
Claim 16
Dependent Claim
104 words
A MOS transistor output circuit, comprising: an input terminal; an output terminal; a first potential point; a first MOS transistor of a first conductivity type having a control electrode connected to said input terminal, and first and second current electrodes; a second MOS transistor of the first conductivity type having a control electrode, a first current electrode, and a second current electrode connected to said control electrode thereof; and a first switch connected between said first and second current electrodes of said second MOS transistor, said first and second MOS transistors being connected in series between said first potential point and said output terminal.
Claim 17
Dependent Claim
63 words
The MOS transistor output circuit of claim 14, wherein said first current electrode of said first MOS transistor is connected to said second current electrode of said second MOS transistor, and said second current electrode of said first MOS transistor is connected to said output terminal, and said first current electrode of said second MOS transistor is connected to said first potential point.
Claim 18
Dependent Claim
102 words
The MOS transistor output circuit of claim 14, further comprising: a second potential point; a third MOS transistor of a second conductivity type having a control electrode connected to said input terminal, and first and second current electrodes; a fourth MOS transistor of the second conductivity type having a control electrode, a first current electrode, and a second current electrode connected to said control electrode thereof; and a second switch connected between said first and second current electrodes of said fourth MOS transistor, said third and fourth MOS transistors being connected in series between said second potential point and said output terminal.
Claim 19
Dependent Claim
121 words
A MOS transistor output circuit, comprising: an input terminal receiving an input signal; an output terminal; a first potential point; a first MOS transistor of a first conductivity type having a first current electrode connected to said first potential point, a second current electrode connected to said output terminal, and a control electrode capable of being connected to said input terminal; a second MOS transistor of a second conductivity type having a first current electrode connected to said output terminal, a second current electrode connected to said first potential point, and a control electrode receiving a logically inverted signal of said input signal; and first control means for determining whether to permit only said first MOS transistor to conduct or not.
Claim 20
Dependent Claim
121 words
A MOS transistor output circuit, comprising: an input terminal receiving an input signal; an output terminal; a first potential point; a first MOS transistor of a first conductivity type having a first current electrode connected to said first potential point, a second current electrode connected to said output terminal, and a control electrode capable of being connected to said input terminal; a second MOS transistor of a second conductivity type having a first current electrode connected to said output terminal, a second current electrode connected to said first potential point, and a control electrode receiving a logically inverted signal of said input signal; and first control means for determining whether to permit only said first MOS transistor to conduct or not.
Claim 21
Dependent Claim
35 words
The MOS transistor output circuit of claim 17, further comprising: an inverter having an input end connected to said input terminal, and an output end connected to said control electrode of said second MOS transistor.
Claim 22
Dependent Claim
68 words
The MOS transistor output circuit of claim 17, wherein said control electrode of said first MOS transistor is capable of being connected to said input terminal through said first control means, and said first control means having a common terminal connected to said control electrode of said first MOS transistor, a first terminal connected to said first potential point, and a second terminal connected to said input terminal.
Claim 23
Dependent Claim
148 words
The MOS transistor output circuit of claim 19, further comprising: a second potential point; a third MOS transistor of the second conductivity type having a first current electrode connected to said second potential point, a second current electrode connected to said output terminal, and a control electrode capable of being connected to said input terminal; a fourth MOS transistor of the first conductivity type having a first current electrode connected to said output terminal, a second current electrode connected to said second potential point; and a control electrode receiving a logically inverted signal of said input signal; and second control means connected between said control electrode of said third MOS transistor and said input terminal and having a common terminal connected to said control electrode of said third MOS transistor, a first terminal connected to said second potential point, and a second terminal connected to said input terminal.
Claim 24
Dependent Claim
121 words
A MOS transistor output circuit, comprising: an input terminal receiving an input signal; an output terminal; a first potential point; a first MOS transistor of a first conductivity type having a first current electrode connected to said first potential point, a second current electrode capable of being connected to said output terminal, and a control electrode connected to said input terminal; a second MOS transistor of a second conductivity type having a first current electrode connected to said output terminal, a second current electrode connected to said first potential point, and a control electrode receiving a logically inverted signal of said input signal; and first control means for determining whether to permit only said first MOS transistor to conduct or not.
Claim 25
Dependent Claim
121 words
A MOS transistor output circuit, comprising: an input terminal receiving an input signal; an output terminal; a first potential point; a first MOS transistor of a first conductivity type having a first current electrode connected to said first potential point, a second current electrode capable of being connected to said output terminal, and a control electrode connected to said input terminal; a second MOS transistor of a second conductivity type having a first current electrode connected to said output terminal, a second current electrode connected to said first potential point, and a control electrode receiving a logically inverted signal of said input signal; and first control means for determining whether to permit only said first MOS transistor to conduct or not.
Claim 26
Dependent Claim
35 words
The MOS transistor output circuit of claim 21, further comprising: an inverter having an input end connected to said input terminal, and an output end connected to said control electrode of said second MOS transistor.
Claim 27
Dependent Claim
41 words
The MOS transistor output circuit of claim 21, wherein said second current electrode of said first MOS transistor is capable of being connected to said output terminal through said first control means, and said first control means includes a first switch.
Claim 28
Dependent Claim
121 words
The MOS transistor output circuit of claim 23, further comprising: a second potential point; a third MOS transistor of the second conductivity type having a first current electrode connected to said second potential point, a second current electrode capable of being connected to said output terminal, and a control electrode connected to said input terminal; a fourth MOS transistor of the first conductivity type having a first current electrode connected to said output terminal, a second current electrode connected to said second potential point, and a control electrode receiving a logically inverted signal of said input signal; and second control means connected between said second current electrode of said third MOS transistor and said output terminal and including a second switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |