Method of extracting layout parasitics for nets of an integrated circuit using a connectivity-based approach

Claim 1

A method of designing an integrated circuit comprising the steps of: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting layout parasitics for at least one of said plurality of nets by using said connectivity-based database comprising the steps of: selecting at least one net from said plurality of nets; in said programmed digital computer, decomposing said at least one selected net into polygon subsections; from said decomposed polygon subsections, determining layout parasitics for one of said at least one selected net of said design schematic of said plurality of nets; and repeating said step of determining layout parasitics until layout parasitics for said at least one selected net of said design schematic have been calculated; and designing said integrated circuit.

Claim 2

A method of designing an integrated circuit comprising the steps of: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting layout parasitics for at least one of said plurality of nets by using said connectivity-based database comprising the steps of: selecting at least one net from said plurality of nets; in said programmed digital computer, decomposing said at least one selected net into polygon subsections; from said decomposed polygon subsections, determining layout parasitics for one of said at least one selected net of said design schematic of said plurality of nets; and repeating said step of determining layout parasitics until layout parasitics for said at least one selected net of said design schematic have been calculated; and designing said integrated circuit.

Claim 4

A method of designing an integrated circuit comprising the steps of: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting layout parasitics for at least one of said plurality of nets by using said connectivity-based database comprising the steps of: selecting a net from said plurality of nets of said design schematic; determining layout resistance parasitics for said selected net of said plurality of nets of said design schematic; determining layout capacitance parasitics for said selected net of said plurality of nets of said design schematic; and repeating said steps of determining layout resistance parasitics and determining capacitance parasitics until parasitics for nets of said design schematic have been extracted; and designing said integrated circuit.

Claim 5

A method of designing an integrated circuit comprising the steps of: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting layout parasitics for at least one of said plurality of nets by using said connectivity-based database comprising the steps of: selecting a net from said plurality of nets of said design schematic; determining layout resistance parasitics for said selected net of said plurality of nets of said design schematic; determining layout capacitance parasitics for said selected net of said plurality of nets of said design schematic; and repeating said steps of determining layout resistance parasitics and determining capacitance parasitics until parasitics for nets of said design schematic have been extracted; and designing said integrated circuit.

Claim 6

A method of extracting layout parasitics for an integrated circuit comprising the steps of: selecting at least one net from a plurality of nets; generating a parasitic structure representation for said selected net from said plurality of nets; comparing said parasitic structure representation against a plurality of predefined structures in a predefined geometry library, said predefined geometry library containing a plurality of predefined parasitic values for said plurality of predefined structures; and selecting as an extracted parasitic value, one of said plurality of predefined values from said predefined geometry library if said parasitic structure representation is similar to one of said plurality of predefined structures.

Claim 7

A method of extracting layout parasitics for an integrated circuit comprising the steps of: selecting at least one net from a plurality of nets; generating a parasitic structure representation for said selected net from said plurality of nets; comparing said parasitic structure representation against a plurality of predefined structures in a predefined geometry library, said predefined geometry library containing a plurality of predefined parasitic values for said plurality of predefined structures; and selecting as an extracted parasitic value, one of said plurality of predefined values from said predefined geometry library if said parasitic structure representation is similar to one of said plurality of predefined structures.

Claim 11

A method of extracting layout parasitics for an integrated circuit comprising the steps of: selecting at least one net from said plurality of nets; generating a cross-sectional structure for said selected net from a connectivity-based database; using said connectivity-based database, generating a signature value for said cross-sectional structure; comparing said signature value against a plurality of predefined signature values in a capacitance synthesis table, said capacitance synthesis table containing said plurality of predefined signature values for a plurality of predefined capacitance values; and selecting as an extracted parasitic capacitance value one of said plurality of predefined capacitance values from said capacitance synthesis table if said signature value is similar to one of said plurality of predefined signature values.

Claim 12

A method of extracting layout parasitics for an integrated circuit comprising the steps of: selecting at least one net from said plurality of nets; generating a cross-sectional structure for said selected net from a connectivity-based database; using said connectivity-based database, generating a signature value for said cross-sectional structure; comparing said signature value against a plurality of predefined signature values in a capacitance synthesis table, said capacitance synthesis table containing said plurality of predefined signature values for a plurality of predefined capacitance values; and selecting as an extracted parasitic capacitance value one of said plurality of predefined capacitance values from said capacitance synthesis table if said signature value is similar to one of said plurality of predefined signature values.

Claim 14

A method of designing an integrated circuit further comprising the steps of: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting layout parasitics for at least one of said plurality of nets by using said connectivity-based database comprising the steps of: selecting at least one net from said plurality of nets; in said programmed digital computer, decomposing said at least one selected net into polygon subsections; from said decomposed polygon subsections, determining layout parasitics for one of said at least one selected net of said design schematic of said plurality of nets; and repeating said step of determining layout parasitics until layout parasitics for said at least one selected net of said design schematic have been calculated; designing said integrated circuit; and fabricating said integrated circuit.

Claim 15

A method of designing an integrated circuit further comprising the steps of: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting layout parasitics for at least one of said plurality of nets by using said connectivity-based database comprising the steps of: selecting at least one net from said plurality of nets; in said programmed digital computer, decomposing said at least one selected net into polygon subsections; from said decomposed polygon subsections, determining layout parasitics for one of said at least one selected net of said design schematic of said plurality of nets; and repeating said step of determining layout parasitics until layout parasitics for said at least one selected net of said design schematic have been calculated; designing said integrated circuit; and fabricating said integrated circuit.

Claim 16

A method of designing an integrated circuit comprising the steps of: inputting a circuit schematic into a programmed digital computer; creating a circuit schematic database from said design schematic using said programmed digital computer; inputting a layout representation of said circuit schematic into said programmed digital computer; creating a layout database from said layout representation using said programmed digital computer; in said programmed digital computer, creating a connectivity-based database from said circuit schematic database and said layout database, wherein said connectivity-based database comprises a plurality of geometries of said layout database that are referenced by a plurality of nets of said circuit schematic; selecting at least one net from said plurality of nets of said circuit schematic; and in said programmed digital computer, extracting layout parasitics for said selected net using said connectivity-based database, wherein said extracting step comprises the steps of: using said connectivity-based database, determining parasitic resistances for said selected net of said circuit schematic; using said connectivity-based database, determining parasitic capacitances for said selected net of said circuit schematic; and repeating said step of determining parasitic resistances and step of determining parasitic capacitances until parasitics for said selected net have been extracted.

Claim 17

A method of designing an integrated circuit comprising the steps of: inputting a circuit schematic into a programmed digital computer; creating a circuit schematic database from said design schematic using said programmed digital computer; inputting a layout representation of said circuit schematic into said programmed digital computer; creating a layout database from said layout representation using said programmed digital computer; in said programmed digital computer, creating a connectivity-based database from said circuit schematic database and said layout database, wherein said connectivity-based database comprises a plurality of geometries of said layout database that are referenced by a plurality of nets of said circuit schematic; selecting at least one net from said plurality of nets of said circuit schematic; and in said programmed digital computer, extracting layout parasitics for said selected net using said connectivity-based database, wherein said extracting step comprises the steps of: using said connectivity-based database, determining parasitic resistances for said selected net of said circuit schematic; using said connectivity-based database, determining parasitic capacitances for said selected net of said circuit schematic; and repeating said step of determining parasitic resistances and step of determining parasitic capacitances until parasitics for said selected net have been extracted.

Claim 19

A method of extracting layout parasitics for an integrated circuit, said method comprising: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting parasitic capacitance data for at least one of said plurality of nets by using said connectivity-based database comprising: selecting a net from said plurality of nets of said design schematic; determining geometries for said selected net from said connectivity-based database; reading a capacitance synthesis table having predefined parasitic capacitance values for predefined capacitance structures; comparing said geometries for said selected net against said predefined capacitance structures in said capacitance synthesis table; and selecting one of said predefined parasitic capacitance values if said geometries for said selected net match one of said predefined capacitance structures; and repeating said extracting parasitic capacitance data until parasitics for nets of said design schematic have been extracted.

Claim 20

A method of extracting layout parasitics for an integrated circuit, said method comprising: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting parasitic capacitance data for at least one of said plurality of nets by using said connectivity-based database comprising: selecting a net from said plurality of nets of said design schematic; determining geometries for said selected net from said connectivity-based database; reading a capacitance synthesis table having predefined parasitic capacitance values for predefined capacitance structures; comparing said geometries for said selected net against said predefined capacitance structures in said capacitance synthesis table; and selecting one of said predefined parasitic capacitance values if said geometries for said selected net match one of said predefined capacitance structures; and repeating said extracting parasitic capacitance data until parasitics for nets of said design schematic have been extracted.

Claim 21

A method of extracting layout parasitics for an integrated circuit, said method comprising: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting parasitic resistance data for at least one of said plurality of nets by using said connectivity-based database comprising: selecting a net from said plurality of nets of said design schematic; determining geometries for said selected net from said connectivity-based database; reading a resistance geometry library having predefined parasitic resistance values for predefined resistance structures; comparing said geometries for said selected net against said predefined resistance structures in said resistance geometry library; and selecting one of said predefined parasitic resistance values if said geometries for said selected net match one of said predefined resistance structures; and repeating said extracting parasitic resistance data until parasitics for nets of said design schematic have been extracted; and designing said integrated circuit.

Claim 22

A method of extracting layout parasitics for an integrated circuit, said method comprising: inputting a design schematic into a programmed digital computer; inputting a layout representation of said design schematic into said programmed digital computer; in said programmed digital computer, creating a connectivity-based database wherein a plurality of geometries in said layout representation are referenced by a plurality of nets of said design schematic; in said programmed digital computer, extracting parasitic resistance data for at least one of said plurality of nets by using said connectivity-based database comprising: selecting a net from said plurality of nets of said design schematic; determining geometries for said selected net from said connectivity-based database; reading a resistance geometry library having predefined parasitic resistance values for predefined resistance structures; comparing said geometries for said selected net against said predefined resistance structures in said resistance geometry library; and selecting one of said predefined parasitic resistance values if said geometries for said selected net match one of said predefined resistance structures; and repeating said extracting parasitic resistance data until parasitics for nets of said design schematic have been extracted; and designing said integrated circuit.