Method and apparatus for forming layout pattern of semiconductor integrated circuit

Claim 1

A method of forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising: a step of receiving logical information; a step of automatically forming the layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; and a step of automatically reforming the layout pattern forming a reformed layout pattern by only performing the routing process, when required logical information is the same as existing logical information and a required layout pattern is also the same as an existing layout pattern at the transistor-constitution level, using connection information and layout information of said existing layout pattern.

Claim 2

A method of forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising: a step of receiving logical information; a step of automatically forming the layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; and a step of automatically reforming the layout pattern forming a reformed layout pattern by only performing the routing process, when required logical information is the same as existing logical information and a required layout pattern is also the same as an existing layout pattern at the transistor-constitution level, using connection information and layout information of said existing layout pattern.

Claim 11

A method of forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising: a step of receiving logical information; a step of automatically forming the layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; and a step of automatically reforming the layout pattern forming a reformed layout pattern without analyzing the logical information down to the transistor-constitution level, when required logical information is the same as existing logical information but a required layout pattern is not the same as an existing layout pattern at the transistor-constitution level, using connection information of said existing layout pattern.

Claim 12

A method of forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising: a step of receiving logical information; a step of automatically forming the layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; and a step of automatically reforming the layout pattern forming a reformed layout pattern without analyzing the logical information down to the transistor-constitution level, when required logical information is the same as existing logical information but a required layout pattern is not the same as an existing layout pattern at the transistor-constitution level, using connection information of said existing layout pattern.

Claim 19

An apparatus for forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising: means for receiving logical information and inputting said logical information to a cell generator; means for automatically forming a layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; first reforming means for automatically reforming the layout pattern forming a reformed layout pattern by only performing the routing process, when required logical information is the same as existing logical information and a required layout pattern is also the same as an existing layout pattern at the transistor-constitution level, using connection information and layout information of said exiting layout pattern; and second reforming means for automatically reforming the layout pattern forming the reformed layout pattern without analyzing the logical information down to the transistor-constitution level, when the required logical information is the same as the existing logical information but the required layout pattern is not the same as the existing layout pattern at the transistor-constitution level, using connection information of said existing layout pattern.

Claim 20

An apparatus for forming a layout pattern of a semiconductor integrated circuit having regular transistor constitutions, said method comprising: means for receiving logical information and inputting said logical information to a cell generator; means for automatically forming a layout pattern by performing a placement process for determining relative positions of transistors and a routing process for determining wiring connections of the transistors at a transistor-constitution level; first reforming means for automatically reforming the layout pattern forming a reformed layout pattern by only performing the routing process, when required logical information is the same as existing logical information and a required layout pattern is also the same as an existing layout pattern at the transistor-constitution level, using connection information and layout information of said exiting layout pattern; and second reforming means for automatically reforming the layout pattern forming the reformed layout pattern without analyzing the logical information down to the transistor-constitution level, when the required logical information is the same as the existing logical information but the required layout pattern is not the same as the existing layout pattern at the transistor-constitution level, using connection information of said existing layout pattern.