US4644187A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate array basic cell
Assignee: Toshiba Corp
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Filing: 1984-12-14
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Granted: 1987-02-17
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Expires: 2004-12-14
Abstract
Abstract There is disclosed a semiconductor integrated circuit device in which the gate of a MOSFET of one circuit of the P channel MOSFET is connected to the gate of a MOSFET of the other circuit of the P channel MOSFET, and the gate of a MOSFET of one circuit of the N channel MOSFET is connected to the gate of a MOSFET of the other circuit of the N channel MOSFET.
Inventors
- 👤 Yasutaka Haji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
144 words
A semiconductor integrated circuit device having gate array structure comprising a plurality of basic cells arranged in a predetermined pattern, each of the basic cells comprising first, second, third and fourth MOSFET series paths, wherein each of the first and second MOSFET series paths comprises a plurality of MOSFET channels of a first channel type connected in series; each of the third and fourth MOSFET series paths comprises a plurality of MOSFET channels of a second channel type connected in series; a gate of each of the MOSFETs of the first MOSFET series path is connected to the gate of a corresponding one of the MOSFETs of the second MOSFET series path; and a gate of each of the MOSFETs of the third MOSFET series path is connected to the gate of a corresponding one of the MOSFETs of the fourth MOSFET series path.
Claim 2
Dependent Claim
144 words
A semiconductor integrated circuit device having gate array structure comprising a plurality of basic cells arranged in a predetermined pattern, each of the basic cells comprising first, second, third and fourth MOSFET series paths, wherein each of the first and second MOSFET series paths comprises a plurality of MOSFET channels of a first channel type connected in series; each of the third and fourth MOSFET series paths comprises a plurality of MOSFET channels of a second channel type connected in series; a gate of each of the MOSFETs of the first MOSFET series path is connected to the gate of a corresponding one of the MOSFETs of the second MOSFET series path; and a gate of each of the MOSFETs of the third MOSFET series path is connected to the gate of a corresponding one of the MOSFETs of the fourth MOSFET series path.
Claim 3
Dependent Claim
49 words
A semiconductor integrated circuit device according to claim 1, wherein: the number of said MOSFETs constituting each of the first, second, third and fourth MOSFET series paths, is two, and said first channel type is an N channel type and said second channel type is a P channel type.
Claim 4
Dependent Claim
49 words
A semiconductor integrated circuit device according to claim 1, wherein: the number of said MOSFETs constituting each of the first, second, third and fourth MOSFET series paths, is three; and said first channel type is an N channel type and said second channel type is a P channel type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-16 | 1990-08-18 | 1991-02-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-16 | 1994-08-18 | 1995-02-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-16 | 1998-08-18 | 1999-02-17 | $7700.00 | Window Closed / Lapsed |