US5351197A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for designing the layout of a subcircuit in an integrated circuit
Assignee: Cascade Design Automation Corp
•
Filing: 1992-01-21
•
Granted: 1994-09-27
•
Expires: 2012-01-21
Abstract
Abstract A method and apparatus for determining integrated circuit layouts of a random access memory (RAM) from a virtual circuit description and specification of a process technology. Starting with high-level descriptions of a circuit, a virtual geometric description of the circuit is developed in terms of reference points relative to a substrate surface. When the process technology is specified, the relationships among the reference points is determined, as in the layout of the RAM. These relationships account for variable sizing of circuit features and pitch matching of circuit features. A connectivity model and a simulation model of the RAM are also produced by the method and apparatus. These model can be used to verify that the RAM is connected as desired and has the desired performance.
Inventors
- 👤 Michael D. Upton
- 👤 Thomas F. Rossman
- 👤 Dean P. Frazier
- 👤 Jay S. Fuller
- 👤 Kendall C. Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:54
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; H; H10; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
131 words
A computer implemented method for designing the layout of a subcircuit on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the subcircuit including internal cells and the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the method comprising the steps of: a. establishing the constraints among the layers of circuit features that are determined by the specified process technology; b. creating a description of a layout geometry for the subcircuit according to the constraints; c. using a computer to generate one or more simulation models for the described layout geometry; and d. using a computer to generate a connectivity test model for the described layout geometry.
Claim 2
Dependent Claim
131 words
A computer implemented method for designing the layout of a subcircuit on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the subcircuit including internal cells and the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the method comprising the steps of: a. establishing the constraints among the layers of circuit features that are determined by the specified process technology; b. creating a description of a layout geometry for the subcircuit according to the constraints; c. using a computer to generate one or more simulation models for the described layout geometry; and d. using a computer to generate a connectivity test model for the described layout geometry.
Claim 3
Independent Claim
17 words
The method of claim I wherein step b further includes sizing the internal cells to optimize performance.
Claim 4
Dependent Claim
148 words
A computer implemented method for designing the layout of a random access memory on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the random access memory including internal cells, such as one or more sense amplifiers, internal buffers and power rails, the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the method comprising the steps of: a. establishing the constraints among the layers of circuit features that are determined by the specified process technology; b. creating a description of a layout geometry for the random access memory according to the constraints; c. using a computer to generate one or more simulation models for the described layout geometry; and d. using a computer to generate a connectivity test model for the described layout geometry.
Claim 5
Dependent Claim
148 words
A computer implemented method for designing the layout of a random access memory on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the random access memory including internal cells, such as one or more sense amplifiers, internal buffers and power rails, the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the method comprising the steps of: a. establishing the constraints among the layers of circuit features that are determined by the specified process technology; b. creating a description of a layout geometry for the random access memory according to the constraints; c. using a computer to generate one or more simulation models for the described layout geometry; and d. using a computer to generate a connectivity test model for the described layout geometry.
Claim 6
Dependent Claim
20 words
The method of claim 3 wherein step b further includes pitch matching the internal cells of the random access memory.
Claim 7
Dependent Claim
17 words
The method of claim 3 wherein step b further includes sizing the internal buffers to optimize performance.
Claim 8
Dependent Claim
17 words
The method of claim 3 wherein step b further includes sizing the power rails to increase reliability.
Claim 9
Dependent Claim
25 words
The method of claim 3 wherein step c further includes sizing the sense amplifiers to maximize operating margins and speed of the random access memory.
Claim 10
Dependent Claim
22 words
The method of claim 3 wherein step c further includes calculating internal operating points of sense amplifiers in the random access memory.
Claim 11
Dependent Claim
201 words
A computer based apparatus for designing the layout of a subcircuit on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the subcircuit including internal cells and the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the apparatus comprising: means for electronically inputting into a computer the circuit feature positions, a plurality of variables, each variable functionally corresponding to a constraint among the layers of circuit features, and a plurality of constants, each constant corresponding to a specific value for one of the variables; memory storage means operatively associated with the means for electronically inputting for storing descriptions of the circuit feature positions, the plurality of variables, and the plurality of constants; and computer processing means operatively associated with the means for electronically inputting and the memory storage means for establishing the constraints that are determined by the specified process technology, for creating a layout geometry for the subcircuit according to the constraints, for generating one or more simulation models for the described layout geometry and for generating a connectivity test model for the described layout geometry.
Claim 12
Dependent Claim
201 words
A computer based apparatus for designing the layout of a subcircuit on an integrated circuit, the layout comprising one or more layers of circuit features subject to one or more constraints, including geometric constraints, the subcircuit including internal cells and the layers being formed with respect to a two-dimensional surface of a substrate in accordance with a specified process technology, the apparatus comprising: means for electronically inputting into a computer the circuit feature positions, a plurality of variables, each variable functionally corresponding to a constraint among the layers of circuit features, and a plurality of constants, each constant corresponding to a specific value for one of the variables; memory storage means operatively associated with the means for electronically inputting for storing descriptions of the circuit feature positions, the plurality of variables, and the plurality of constants; and computer processing means operatively associated with the means for electronically inputting and the memory storage means for establishing the constraints that are determined by the specified process technology, for creating a layout geometry for the subcircuit according to the constraints, for generating one or more simulation models for the described layout geometry and for generating a connectivity test model for the described layout geometry.
References Cited (Backward Citations)
US3653071A
Cited
US4613940A
Cited
US4600995A
Cited
US4580228A
Cited
US4554625A
Cited
US4630219A
Cited
US4615011A
Cited
US4651284A
Cited
US4635208A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-09-26 | 1998-03-28 | 1998-09-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-09-26 | 2002-03-28 | 2002-09-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-09-26 | 2006-03-28 | 2006-09-27 | $7700.00 | Window Closed / Lapsed |