System and method for synthesizing logic circuits with timing constraints

Claim 3

The method of claim 1 wherein said determining step includes computing said capacitance values so as to minimize a routing difficulty value.

Claim 4

The method of claim 2 wherein said routing difficulty value comprises a sum of routing difficulty values associated with each of said nodes in said integrated circuit.

Claim 7

The method of claim 4 further including: repeating the following steps until changes in said computed routing difficulty value meet predefined criteria: selecting one of said components; decreasing said time delay and maximum capacitance value associated with a node coupled to an output port of said component and increasing by corresponding amounts said time delay and maximum capacitance value associated with nodes coupled to input ports of said component; recomputing said routing difficulty value; and retaining said changed time delay and maximum capacitance values only if said recomputed routing difficulty value is smaller than its previous value.

Claim 8

A computer aided design system for improving the timing performance of an integrated circuit, comprising: first input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; second input means and storage means for receiving and storing in a computer memory a plurality of timing constraints, each of said timing constraints including a first node and a second node of said circuit and a maximum delay for a signal to propagate from said first node to said second node; means for determining capacitance values for individual nodes of said nodes of said circuit so as to meet said timing constraints; and means for passing said netlist and capacitance values to a silicon compiler for automatically placing/routing a circuit having said components and interconnection nodes with capacitance values not exceeding said capacitance values.

Claim 9

A computer aided design system for improving the timing performance of an integrated circuit, comprising: first input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components; each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit; second input means and storage means for receiving and storing in a computer memory a plurality of timing constraints, each of said timing constraints including a first node and a second node of said circuit and a maximum delay for a signal to propagate from said first node to said second node; means for determining capacitance values for individual nodes of said nodes of said circuit so as to meet said timing constraints; and means for passing said netlist and capacitance values to a silicon compiler for automatically placing/routing a circuit having said components and interconnection nodes with capacitance values not exceeding said capacitance values.

Claim 10

The apparatus of claim 6 wherein said determining means includes means for computing said capacitance values so as to minimize a routing difficulty value.

Claim 11

The apparatus of claim 7 wherein said routing difficulty value comprises a sum of routing difficulty values associated with each of said nodes in said integrated circuit.

Claim 12

A computer aided design system for improving the timing performance of an integrated circuit, comprising: input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in a specified integrated circuit and a set of nodes interconnecting said components; each said component of said specified integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said specified integrated circuit; initial value assignment means, coupled to said storage means, for assigning an initial capacitance value to each said node; layout difficulty function means for computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said specified integrated circuit; means for adjusting said capacitance values for said specified integrated circuit so as to reduce said computed routing difficulty value; means for altering said capacitance values so as to meet timing constraints; and means for passing said netlist and adjusted capacitance values to a silicon compiler to automatically place/route a circuit having said components and interconnection nodes with capacitance values not exceeding said adjusted capacitance values.

Claim 13

A computer aided design system for improving the timing performance of an integrated circuit, comprising: input means and storage means for receiving and storing in a computer memory a netlist denoting a list of components in a specified integrated circuit and a set of nodes interconnecting said components; each said component of said specified integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said specified integrated circuit; initial value assignment means, coupled to said storage means, for assigning an initial capacitance value to each said node; layout difficulty function means for computing a routing difficulty value, comprising a sum of routing difficulty values associated with each of said nodes in said specified integrated circuit; means for adjusting said capacitance values for said specified integrated circuit so as to reduce said computed routing difficulty value; means for altering said capacitance values so as to meet timing constraints; and means for passing said netlist and adjusted capacitance values to a silicon compiler to automatically place/route a circuit having said components and interconnection nodes with capacitance values not exceeding said adjusted capacitance values.

Claim 14

The computer aided design system of claim 9 further including: optimization means, coupled to said initial value assignment means, said storage means, and said layout difficulty function means for repeatedly: selecting one of said components; decreasing said time delay and maximum capacitance value associated with a node coupled to an output port of said component and increasing by corresponding amounts said time delay and maximum capacitance value associated with nodes coupled to input ports of said component; calling said layout difficulty function means to recompute said routing difficulty value; and retaining said changed time delay and maximum capacitance values only if said recomputed routing difficulty value is smaller than its previous value; whereby said maximum capacitance values for said specified integrated circuit are automatically adjusted so as to reduce the difficulty of routing connections between said specified integrated circuit's components.