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US5899705A Expired / Lapsed US ⏱️ 0.0 years remaining

Stacked leads-over chip multi-chip module

Assignee: Round Rock Research LLC
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Filing: 1998-04-30
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Granted: 1999-05-04
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Expires: 2018-04-30
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Abstract

Abstract A multi-chip module (MCM) and method of manufacturing is disclosed that provides for attachment of semiconductor dice to both sides of the MCM printed circuit board (PCB). Semiconductor dice attached to the top surface of the PCB may be attached by conventional wire bonding, TAB or flip chip methods whereas those semiconductor dice attached to the bottom surface of the PCB are wire bonded or TAB connected to the top surface through openings in the PCB. The openings provide a lead-over-chip (LOC) arrangement for those semiconductor dice attached to the bottom surface resulting in shortened wire bonds. The bottom surface of the PCB may be provided with die recesses into which the openings extend, to receive the dice and bring their active surfaces even closer to the top surface of the PCB for wire bonding.

Inventors

  • 👤 Salman Akram

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 11:36
CPC Classifications
H; H10; H10W; H10W99/00; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/63; H10W70/635; H10W70/67; H10W70/68; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W90/00; H10W70/682; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/075; H10W72/20; H10W72/29; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/853; H10W72/865; H10W72/874; H10W72/884; H10W72/90; H10W72/941; H10W72/944; H10W72/9445; H10W74/15; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T408/00; Y10T408/55; Y10T408/563; Y10T408/5635

Claims Analysis

Total Claims: 18
Claim 1
Independent Claim 129 words
A method of manufacturing a multi-chip module, comprising: providing a substrate having a top surface and a bottom surface, at least one opening therethrough, and a plurality of conductive areas on said top surface; attaching at least one semiconductor die having a plurality of bond pads on an active surface thereof adjacent said bottom surface of said substrate such that said bond pads are exposed through said at least one opening; connecting at least one of said bond pads to at least one of said conductive areas with an intermediate conductive element; attaching at least one semiconductor die to said top surface of said substrate; and electrically connecting said at least one semiconductor die attached to said top surface to at least another of said plurality of conductive areas.
Claim 2
Independent Claim 129 words
A method of manufacturing a multi-chip module, comprising: providing a substrate having a top surface and a bottom surface, at least one opening therethrough, and a plurality of conductive areas on said top surface; attaching at least one semiconductor die having a plurality of bond pads on an active surface thereof adjacent said bottom surface of said substrate such that said bond pads are exposed through said at least one opening; connecting at least one of said bond pads to at least one of said conductive areas with an intermediate conductive element; attaching at least one semiconductor die to said top surface of said substrate; and electrically connecting said at least one semiconductor die attached to said top surface to at least another of said plurality of conductive areas.
Claim 3
Dependent Claim 27 words
The method of claim 1, wherein said connecting said at least one bond pad to said at least one conductive area comprises wire bonding or TAB attachment.
Claim 4
Dependent Claim 31 words
The method of claim 1, wherein said electrically connecting said at least one semiconductor die attached to said top surface is effected by wire bonding, TAB attachment or flip chip bonding.
Claim 5
Dependent Claim 25 words
The method of claim 1, further including forming a wall around at least a portion of a perimeter of said top surface of said substrate.
Claim 6
Dependent Claim 13 words
The method of claim 4, further including attaching a lid to said wall.
Claim 7
Dependent Claim 27 words
The method of claim 4, further including contacting at least a portion of said at least one semiconductor die attached to said top surface with said lid.
Claim 8
Dependent Claim 25 words
The method of claim 1, further including forming a wall around at least a portion of a perimeter of said bottom surface of said substrate.
Claim 9
Dependent Claim 13 words
The method of claim 7, further including attaching a lid to said wall.
Claim 10
Dependent Claim 27 words
The method of claim 8, further including contacting at least a portion of said at least one semiconductor die attached adjacent said bottom surface with said lid.
Claim 11
Dependent Claim 21 words
The method of claim 1, further including encapsulating at least said at least one semiconductor die attached to said top surface.
Claim 12
Dependent Claim 24 words
The method of claim 1, further comprising attaching said at least one semiconductor die to said top surface over said at least one opening.
Claim 13
Dependent Claim 27 words
The method of claim 1, further including introducing a non-conductive underfill between said at least one semiconductor die attached to said top surface and said top surface.
Claim 14
Dependent Claim 38 words
The method of claim 12, further including disposing said at least one semiconductor die attached to said top surface over said at least one opening, and at least partially filling said at least one opening with said underfill.
Claim 15
Dependent Claim 36 words
The method of claim 1, further including forming said substrate with a recess in said bottom surface and disposing said at least one semiconductor die attached adjacent said bottom surface at least partially within said recess.
Claim 16
Dependent Claim 23 words
The method of claim 14, further including disposing said at least one semiconductor die attached adjacent said bottom surface completely within said recess.
Claim 17
Dependent Claim 26 words
The method of claim 15, further including disposing a lid on said bottom surface and over said at least one semiconductor die disposed in said recess.
Claim 18
Dependent Claim 21 words
The method of claim 1, further including encapsulating at least said at least one semiconductor die attached adjacent said bottom surface.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-05-03 2002-11-02 2003-05-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-05-03 2006-11-02 2007-05-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-05-03 2010-11-02 2011-05-04 $7700.00 Window Closed / Lapsed

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