Patent US5886535A successfully refreshed from Google Patents.
US5886535A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer level burn-in base unit substrate and assembly
Assignee: W.L. Gore and Associates Inc
•
Filing: 1996-11-08
•
Granted: 1999-03-23
•
Expires: 2016-11-08
Abstract
Abstract The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level bum-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.
Inventors
- 👤 John J. Budnaitis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:07
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R1/07307; G01R1/07314; G01R1/0735; G01R31/2886; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126
Claims Analysis
Total Claims: 94
Claim 1
Independent Claim
55 words
A wafer level electrical test substrate comprising: a high planarity base unit having a plurality of first and second terminals disposed on a surface of said high planarity base unit, said second terminals to be connected with an electrical test signal generator, and said first terminals to be connected with conductive pads of a wafer.
Claim 2
Dependent Claim
55 words
A wafer level electrical test substrate comprising: a high planarity base unit having a plurality of first and second terminals disposed on a surface of said high planarity base unit, said second terminals to be connected with an electrical test signal generator, and said first terminals to be connected with conductive pads of a wafer.
Claim 3
Dependent Claim
19 words
The substrate according to claim 1, wherein said high planarity base unit further includes alternating conductive and dielectric layers.
Claim 4
Dependent Claim
15 words
The substrate according to claim 1, wherein said base unit covers a 200 mm wafer.
Claim 5
Dependent Claim
19 words
The substrate according to claim 1, wherein said substrate has a planarity of approximately 0.001 inches per linear foot.
Claim 6
Dependent Claim
25 words
The substrate according to claim 1, wherein said base unit is dimensioned to cover a semiconductor wafer between 75 mm and 300 mm in size.
Claim 7
Dependent Claim
17 words
The substrate according to claim 5, wherein said base unit is between 6"×6" and 24"×24" in dimension.
Claim 8
Dependent Claim
18 words
The substrate according to claim 1, wherein said first and second set of terminals are metallic contact pads.
Claim 9
Dependent Claim
50 words
The substrate according to claim 7, wherein said metallic contact pads are formed from a metal selected from the group consisting essentially of copper, nickel, gold, platinum, palladium and cobalt, with a thickness of between 1 μm and 50 μm, and dimensions of 25 μm×25 μm and 250 μm×250 μm.
Claim 10
Dependent Claim
30 words
The substrate according to claim 1, wherein said high planarity base unit further includes: a first signal layer having a plurality of superimposed co-planar conductive segments with interdisposed dielectric layers.
Claim 11
Dependent Claim
29 words
The substrate according to claim 9, wherein said first set of terminals and said second set of terminals are disposed on a lower surface of said first signal layer.
Claim 12
Dependent Claim
19 words
The substrate according to claim 9, wherein said first set of terminals are disposed on said first signal layer.
Claim 13
Dependent Claim
42 words
The substrate according to claim 9, wherein said base unit includes a base having a low coefficient of thermal expansion (CTE), said base being disposed between an uppermost dielectric layer of said first signal layer limiting thermal expansion of said base unit.
Claim 14
Dependent Claim
22 words
The substrate according to claim 12, wherein said low CTE base has a planarity of less than 0.010 inches per linear foot.
Claim 15
Dependent Claim
19 words
The substrate according to claim 12, wherein said low CTE base has a low composite coefficient of thermal expansion.
Claim 16
Dependent Claim
55 words
The substrate according to claim 12, further comprising: a balancing layer disposed against said low CTE base, said balancing layer having a conductive layer disposed against a dielectric layer; and said conductive and dielectric layers of said balancing layer having a density substantially matching said conductive segments and said dielectric of said first signal layer.
Claim 17
Dependent Claim
60 words
The substrate according to claim 12, further comprising a stack of balancing layers, each balancing layer including a conductive layer and a dielectric layer having a density substantially matching a density of a corresponding layer of said high planarity base unit, and said stack of balancing layers being disposed against said low CTE base at one of said dielectric layers.
Claim 18
Dependent Claim
42 words
The substrate according to claim 12, further comprising: a core layer disposed between said low CTE base and said uppermost dielectric layer, said core layer being a substantially continuous conductive sheet and having a dielectric layer disposed against said low CTE base.
Claim 19
Dependent Claim
33 words
The substrate according to claim 17, wherein said substantially continuous conductive sheet of said core layer is made with a sheet of copper that has a thickness between 5 μm and 50 μm.
Claim 20
Dependent Claim
63 words
The substrate according to claim 17, further comprising: a second signal layer, disposed between said core layer and said low CTE base, having a plurality of co-planar conductive segments disposed against said dielectric of said core layer, and said second signal layer including a dielectric disposed between said plurality of co-planar conductive segments of said second signal layer and said low CTE base.
Claim 21
Dependent Claim
20 words
The substrate according to claim 17, wherein said substantially continuous conductive sheet of said core layer is a metallic mesh.
Claim 22
Dependent Claim
39 words
The substrate according to claim 17, further comprising a pad layer having a plurality of said first set of terminals being disposed against a dielectric, said dielectric of said pad layer being disposed against said high planarity base unit.
Claim 23
Dependent Claim
16 words
The substrate according to claim 21, wherein said pad layer is disposed against said core layer.
Claim 24
Dependent Claim
17 words
The substrate according to claim 21, wherein said pad layer is disposed against said first signal layer.
Claim 25
Dependent Claim
43 words
The substrate according to claim 21, wherein at least one of said first set of terminals is individually coupled to a corresponding one of said plurality of co-planar conductive segments with a conductive via through at least said dielectric of said pad layer.
Claim 26
Dependent Claim
29 words
The substrate according to claim 21, wherein said substantially continuous conductive sheet of said core layer is electrically coupled to at least one of said second set of terminals.
Claim 27
Dependent Claim
42 words
The substrate according to claim 25, wherein at least one of said first set of terminals is individually coupled to said substantially continuous conductive sheet of said core layer with a conductive via through at least said dielectric of said pad layer.
Claim 28
Dependent Claim
55 words
The substrate according to claim 12, wherein said low CTE base includes first and second layers of a metal or metal alloy having a low coefficient of thermal expansion with each low CTE metal or metal alloy layer having machined surfaces to have a degree of planarity of less than 0.01 inches per linear foot.
Claim 29
Dependent Claim
22 words
The substrate according to claim 27, wherein each of said low CTE metal or metal alloy layers is approximately 115 mils thick.
Claim 30
Dependent Claim
60 words
The substrate according to claim 27, wherein said low CTE metal or metal alloy layers have a combined thickness t 1 and a chemically distinct intermediate metal or metal alloy layer disposed therebetween which has a thickness t 2 , wherein a ratio t 1 to t 2 matches a coefficient of thermal expansion of a semiconductor wafer +/-3 ppm/°C.
Claim 31
Dependent Claim
37 words
The substrate according to claim 29, wherein said ratio of said low CTE metal or metal alloy layers thickness to said intermediate layer thickness provides a coefficient of thermal expansion that matches a silicon wafer +/-3 ppm/°C.
Claim 32
Dependent Claim
34 words
The substrate according to claim 29, wherein said thickness ratio provides a coefficient of thermal expansion that matches a wafer formed from germanium, silicon germanium, silicon carbide, gallium arsenide, selenium or tellurium +/-3 ppm/°C.
Claim 33
Dependent Claim
37 words
The substrate according to claim 27, wherein said low CTE metal or metal alloy layers are a nickel alloy and said substrate further includes a layer of copper disposed between said first and second nickel alloy layers.
Claim 34
Dependent Claim
20 words
The substrate according to claim 32, wherein said nickel alloy contains between 30 wt. % and 42 wt. % nickel.
Claim 35
Dependent Claim
26 words
The substrate according to claim 32, wherein said nickel alloy has a coefficient of thermal expansion of between about less than 1 to about 4 ppm/°C.
Claim 36
Dependent Claim
30 words
The substrate according to claim 32, wherein said copper layer comprises approximately 10% of the total thickness of said low CTE metal or metal alloy layers and said copper layer.
Claim 37
Dependent Claim
28 words
The substrate according to claim 32, wherein first and second adhesive dielectric layers are respectively disposed between said copper layer and said first and second nickel alloy layers.
Claim 38
Dependent Claim
24 words
The substrate according to claim 36, wherein said first and second adhesive dielectric layers each have a T g of at least 200° C.
Claim 39
Dependent Claim
52 words
The substrate according to claim 36, wherein each of said dielectric layers of said low CTE base has a thickness, when combined with said low CTE metal or metal alloy layers, provides a base with a coefficient of thermal expansion that matches the coefficient of thermal expansion of the wafer +/-3 ppm/°C.
Claim 40
Dependent Claim
28 words
The substrate according to claim 38, wherein a thickness dimension of each of said dielectric layers of said low CTE base is between 25 μm and 250 μm.
Claim 41
Dependent Claim
19 words
The substrate according to claim 36, wherein said dielectric layers include a porous polymer material that supports said adhesive.
Claim 42
Dependent Claim
14 words
The substrate according to claim 40, wherein said porous polymer is a porous polyolefin.
Claim 43
Dependent Claim
16 words
The substrate according to claim 40, wherein said porous polymer is porous polypropylene or porous polyethylene.
Claim 44
Dependent Claim
16 words
The substrate according to claim 40, wherein said porous polymer is a woven or fibrous material.
Claim 45
Dependent Claim
13 words
The substrate according to claim 40, wherein said porous polymer is a fluoropolymer.
Claim 46
Dependent Claim
45 words
The substrate according to claim 40, wherein said adhesive includes a mixture of at least two adhesive components, where the adhesive component is selected from an epoxy resin, an acrylic resin, a urethane resin, a silicone resin, a polyimide resin or a cyanate ester resin.
Claim 47
Dependent Claim
13 words
The substrate according to claim 40, wherein said adhesive is an epoxy resin.
Claim 48
Dependent Claim
13 words
The substrate according to claim 40, wherein said adhesive is an acrylic resin.
Claim 49
Dependent Claim
13 words
The substrate according to claim 40, wherein said adhesive is a urethane resin.
Claim 50
Dependent Claim
13 words
The substrate according to claim 40, wherein said adhesive is a silicone resin.
Claim 51
Dependent Claim
13 words
The substrate according to claim 40, wherein said adhesive is a polyimide resin.
Claim 52
Dependent Claim
14 words
The substrate according to claim 40, wherein said adhesive is a cyanate ester resin.
Claim 53
Dependent Claim
14 words
The substrate according to claim 40, wherein said adhesive also contains a filler mixture.
Claim 54
Dependent Claim
25 words
The substrate according to claim 52, wherein said filler mixture comprises at least 25 wt. % percent of the total weight of said dielectric layer.
Claim 55
Dependent Claim
27 words
The substrate according to claim 52, wherein said filler mixture comprises between 30 wt. % to 90 wt. % of the total weight of said dielectric layer.
Claim 56
Dependent Claim
27 words
The substrate according to claim 52, wherein said filler mixture comprises between 30 wt. % and 70 wt. % of the total weight of said dielectric layer.
Claim 57
Dependent Claim
29 words
The substrate according to claim 52, wherein said filler mixture includes TiO 2 or Al 2 O 3 respectively prepared from the vapor combustion of molten titanium and aluminum.
Claim 58
Dependent Claim
13 words
The substrate according to claim 52, where said filler mixture includes non-conductive carbon.
Claim 59
Dependent Claim
13 words
The substrate according to claim 57, wherein said non-conductive carbon is furnace black.
Claim 60
Dependent Claim
21 words
The substrate according to claim 52, wherein said filler mixture includes SiO 2 prepared from the vapor combustion of molten silicon.
Claim 61
Dependent Claim
14 words
The substrate according to claim 59, wherein said filler mixture also includes non-conductive carbon.
Claim 62
Dependent Claim
13 words
The substrate according to claim 60, wherein said non-conductive carbon is furnace black.
Claim 63
Independent Claim
58 words
A method of forming a wafer level electrical test substrate, comprising: providing a high planarity base; laminating at least one set of alternating conductive and dielectric layers to a lower surface of said base; and laminating at least one balancing layer on an upper surface of said high planarity base to form a wafer level electrical test substrate.
Claim 64
Independent Claim
58 words
A method of forming a wafer level electrical test substrate, comprising: providing a high planarity base; laminating at least one set of alternating conductive and dielectric layers to a lower surface of said base; and laminating at least one balancing layer on an upper surface of said high planarity base to form a wafer level electrical test substrate.
Claim 65
Dependent Claim
19 words
The method according to claim 62, wherein said dielectric layers have a T g of a least 200° C.
Claim 66
Dependent Claim
27 words
The method according to claim 62, wherein said alternating layers include a first signal layer having a plurality of superimposed co-planar conductive segments with interdisposed dielectric layers.
Claim 67
Dependent Claim
78 words
The method according to claim 62, wherein said base providing step includes: providing first and second layers of a metal or metal alloy having a low coefficient of thermal expansion (CTE); machining surfaces of said first and second low CTE metal or metal alloy layers to have a degree of planarity of less than 0.01 inches per linear foot; and laminating said first and second low CTE metal or metal alloy layers to form a low CTE base.
Claim 68
Dependent Claim
25 words
The method according to claim 65, comprising laminating said first and second metal alloy layers to one another by laminating a layer of copper therebetween.
Claim 69
Dependent Claim
60 words
The method according to claim 66, further including the step of selecting said low CTE metal or metal alloy layers to have a combined thickness t 1 and an intermediate copper layer to have a thickness t 2 , whereby a ratio t 1 to t 2 is chosen to match the coefficient of thermal expansion of a semiconductor wafer.
Claim 70
Dependent Claim
22 words
The method according to claim 67, wherein each of said low CTE metal or metal alloy layers is approximately 115 mils thick.
Claim 71
Dependent Claim
39 words
The method according to claim 67, comprising selecting said ratio of said low CTE metal or metal alloy layer thickness to said copper layer thickness to provide a coefficient of thermal expansion that matches a silicon wafer +/-3 ppm/°C.
Claim 72
Dependent Claim
36 words
The method according to claim 67, comprising selecting said thickness ratio to provide a coefficient of thermal expansion that matches a wafer formed from germanium, silicon germanium, silicon carbide, gallium arsenide, selenium or tellurium +/-3 ppm/°C.
Claim 73
Dependent Claim
32 words
The method according to claim 67, wherein said low CTE metal or metal alloys layers are machined to have a planarity of less than or equal to 0.001 inches per linear foot.
Claim 74
Dependent Claim
32 words
The substrate according to claim 67, comprising selecting said copper layer thickness to be 10% of the total thickness of said low CTE metal or metal alloy layers and said copper layer.
Claim 75
Dependent Claim
60 words
The method according to claim 66, wherein said copper laminating step includes first laminating a dielectric material on upper and lowers surfaces of said copper layer to form a dielectric-copper-dielectric laminate, and then locating the dielectric-copper-dielectric laminate between said low CTE metal or metal alloy layers to laminate the low CTE metal or metal alloy layers to said copper layer.
Claim 76
Dependent Claim
74 words
The method according to claim 73, wherein said dielectric layers used to laminate said copper layer to said low CTE metal or metal alloy layers have a selected thickness, so that when combined with said low CTE metal or metal alloy layers and said copper layer provide a low CTE base that has a coefficient of thermal expansion that matches the coefficient of thermal expansion of a semiconductor wafer to be tested, +/-3 ppm/°C.
Claim 77
Dependent Claim
36 words
The method according to claim 73, comprising selecting said dielectric layer used to laminate the copper layer to the low CTE metal or metal alloy layer to have a thickness between 25 μm and 250 μm.
Claim 78
Dependent Claim
20 words
The method according to claim 73, comprising selecting as all of said dielectric layers porous polymers containing an imbibed adhesive.
Claim 79
Dependent Claim
14 words
The method according to claim 76, wherein said porous polymer is a porous polyolefin.
Claim 80
Dependent Claim
13 words
The method according to claim 76, wherein said porous polymer is a fluoropolymer.
Claim 81
Dependent Claim
15 words
The method according to claim 78, wherein said porous fluoropolymer includes at least a polytetrafluoroethylene.
Claim 82
Dependent Claim
12 words
The method according to claim 79, wherein said fluoropolymer is expanded polytetrafluoroethylene.
Claim 83
Dependent Claim
22 words
The method according to claim 76, comprising selecting as a porous polymer, a porous polymer matrix impregnated with an adhesive filler mixture.
Claim 84
Dependent Claim
29 words
The method according to claim 81, wherein said filler mixture includes TiO 2 or Al 2 O 3 respectively prepared from the vapor combustion of molten titanium and aluminum.
Claim 85
Dependent Claim
35 words
The method according to claim 81, comprising selecting as an adhesive at least one of an epoxy resin, an acrylic resin, a urethane resin, a silicon resin, a polyimide resin and a cyanate ester resin.
Claim 86
Dependent Claim
17 words
The method according to claim 81, comprising selecting as an adhesive a mixture of high temperature adhesives.
Claim 87
Dependent Claim
25 words
The method according to claim 81, comprising selecting as said first and second dielectric layers materials having a T g of a least 200° C.
Claim 88
Dependent Claim
21 words
The method according to claim 81, wherein said filler mixture comprises between 25 wt. % and 90 wt. % percent filler.
Claim 89
Dependent Claim
27 words
The method according to claim 86, wherein said filler mixture comprises between 30 wt. % and 70 wt. % of the total weight of said dielectric layer.
Claim 90
Dependent Claim
13 words
The method according to claim 81, where said filler mixture includes non-conductive carbon.
Claim 91
Dependent Claim
13 words
The method according to claim 88, wherein said non-conductive carbon is furnace black.
Claim 92
Dependent Claim
21 words
The method according to claim 81, wherein said filler mixture includes SiO 2 prepared from the vapor combustion of molten silicon.
Claim 93
Dependent Claim
14 words
The method according to claim 90, wherein said filler mixture also includes non-conductive carbon.
Claim 94
Dependent Claim
13 words
The method according to claim 91, wherein said non-conductive carbon is furnace black.
References Cited (Backward Citations)
USRE26837E
Cited
US3609547A
Cited
US3953566A
Cited
US3736471A
Cited
US4133592A
Cited
US4540229A
Cited
US4482516A
Cited
US5315481A
Cited
US4530779A
Cited
US4705762A
Cited
US4683550A
Cited
US4733461A
Cited
US4654248A
Cited
US4840570A
Cited
US5231055A
Cited
US4985296A
Cited
US5034801A
Cited
US5100740A
Cited
US4963225A
Cited
US4968931A
Cited
US5007163A
Cited
US5440240A
Cited
US5252857A
Cited
US5541524A
Cited
DE4231185A1
Cited
JPH05110257A
Cited
US5389885A
Cited
US5461328A
Cited
US5380210A
Cited
US5437556A
Cited
US5428190A
Cited
US5420796A
Cited
US5498467A
Cited
US5602491A
Cited
US5766979A
Cited
US5830565A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-22 | 2002-09-21 | 2003-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-22 | 2006-09-21 | 2007-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-22 | 2010-09-21 | 2011-03-23 | $7700.00 | Window Closed / Lapsed |