US5420796A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of inspecting planarity of wafer surface after etchback step in integrated circuit fabrication
Assignee: Philips Semiconductors Inc
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Filing: 1993-12-23
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Granted: 1995-05-30
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Expires: 2013-12-23
Abstract
Abstract An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.
Inventors
- 👤 Milind Weling
- 👤 Calvin T. Gabriel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:06
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/20; H10P74/203; G; G01; G01Q; G01Q60/00; G01Q60/24; Y; Y10; Y10S; Y10S977/00; Y10S977/84; Y10S977/849; Y10S977/852; Y10S977/854
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
128 words
A method of controlling an integrated circuit fabrication process, comprising the steps of: (a) performing a first step of integrated circuit fabrication on a wafer comprising the step of: forming a first set of one or more material layers on said wafer; and (b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of: scanning a predetermined area of said wafer's surface with an atomic force microscope; gathering surface height data from the atomic force microscope representing height with respect to position; generating from the gathered surface height data at least one signal indicative of surface planarity; comparing the at least one signal with predefined planarity criteria to determine if said forming step produced a surface that meets said predefined planarity criteria,
Claim 2
Independent Claim
128 words
A method of controlling an integrated circuit fabrication process, comprising the steps of: (a) performing a first step of integrated circuit fabrication on a wafer comprising the step of: forming a first set of one or more material layers on said wafer; and (b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of: scanning a predetermined area of said wafer's surface with an atomic force microscope; gathering surface height data from the atomic force microscope representing height with respect to position; generating from the gathered surface height data at least one signal indicative of surface planarity; comparing the at least one signal with predefined planarity criteria to determine if said forming step produced a surface that meets said predefined planarity criteria,
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein: said generating step generates said at least one signal using an arithmetic mean procedure.
Claim 4
Dependent Claim
20 words
The method of claim 1, wherein: said generating step generates said at least one signal using a root mean-square procedure.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein: said generating step generates said at least one signal using a maximum height procedure.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein: said generating step generates said at least one signal using a peak to valley height procedure.
Claim 7
Dependent Claim
19 words
The method of claim 1, wherein: said generating step generates said at least one signal using a roughness procedure.
Claim 8
Dependent Claim
66 words
The method of claim 1, further including: when the at least one signal is above a predetermined threshold, discarding the wafer; when the at least one signal is equal to a predetermined threshold, returning the wafer to a prior step of the integrated circuit fabrication for repair; and when the at least one signal is below a predetermined threshold, continuing with the integrated circuit fabrication process.
Claim 9
Dependent Claim
30 words
The method of claim 1, further including: when the at least one signal is above a predetermined threshold, modifying the fabrication process to increase the quality of subsequent wafer production.
Claim 10
Dependent Claim
24 words
The method of claim 1, wherein: after said second sequence of steps is performed, said first and second sequences of steps are again performed.
Claim 11
Independent Claim
184 words
A method of controlling an integrated circuit fabrication process, comprising the steps of: (a) performing a first sequence of integrated circuit fabrication steps on a wafer comprising the steps of: forming and patterning a first set of one or more material layers on said wafer, wherein the first set of layers is deposited and patterned in such manner to create hills and valleys therein; forming a second set of one or more material layers over said first set of material layers; etching back the deposited second set of material layers to produce a surface on the resulting wafer; (b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of: scanning a predetermined area of said wafer's surface with an atomic force microscope; gathering surface height data from the atomic force microscope representing height with respect to position; generating from the gathered surface height data at least one signal indicative of surface planarity; comparing the at least one signal with predefined planarity criteria to determine if said etching back step produced a surface that meets said predefined planarity criteria.
Claim 12
Independent Claim
184 words
A method of controlling an integrated circuit fabrication process, comprising the steps of: (a) performing a first sequence of integrated circuit fabrication steps on a wafer comprising the steps of: forming and patterning a first set of one or more material layers on said wafer, wherein the first set of layers is deposited and patterned in such manner to create hills and valleys therein; forming a second set of one or more material layers over said first set of material layers; etching back the deposited second set of material layers to produce a surface on the resulting wafer; (b) performing a second sequence of integrated circuit fabrication steps on said wafer comprising the steps of: scanning a predetermined area of said wafer's surface with an atomic force microscope; gathering surface height data from the atomic force microscope representing height with respect to position; generating from the gathered surface height data at least one signal indicative of surface planarity; comparing the at least one signal with predefined planarity criteria to determine if said etching back step produced a surface that meets said predefined planarity criteria.
Claim 13
Dependent Claim
20 words
The method of claim 10, wherein: said generating step generates said at least one signal using an arithmetic mean procedure.
Claim 14
Dependent Claim
19 words
The method of claim 10, wherein: said generating step generates said at least one signal using a roughness procedure.
Claim 15
Dependent Claim
66 words
The method of claim 10, further including: when the at least one signal is above a predetermined threshold, discarding the wafer; when the at least one signal is equal to a predetermined threshold, returning the wafer to a prior step of the integrated circuit fabrication for repair; and when the at least one signal is below a predetermined threshold, continuing with the integrated circuit fabrication process.
Claim 16
Dependent Claim
26 words
The method of claim 10, further including: when the at least one signal is above a predetermined threshold, modifying the fabrication process of subsequent wafer production.
Claim 17
Dependent Claim
24 words
The method of claim 10, wherein: after said second sequence of steps is performed, said first and second sequences of steps are again performed.
Claim 18
Independent Claim
197 words
A method of controlling an integrated circuit fabrication process, comprising the steps of: forming and patterning a first material layer on said wafer, wherein the first material layer is deposited and patterned in such manner to create hills and valleys therein; forming a second material layer over said first material layer; etching back the deposited second material layer to produce a surface on the resulting wafer; scanning a predetermined region of the wafer surface with an atomic force microscope; gathering data from the atomic force microscope representing height with respect to position; generating from the gathered data at least one signal indicative of surface roughness using a predetermined procedure; comparing the at least one signal indicative of surface roughness with predefined criteria; when the at least one signal is below a first predetermined threshold of the predetermined criteria, continuing with the integrated circuit fabrication process; when the at least one signal is within an intermediate range of said first predetermined threshold and a second predetermined threshold of the predetermined criteria, performing a remedial process on the wafer; and when the at least one signal is above said second predetermined threshold of the predetermined criteria, discarding the wafer.
Claim 19
Independent Claim
197 words
A method of controlling an integrated circuit fabrication process, comprising the steps of: forming and patterning a first material layer on said wafer, wherein the first material layer is deposited and patterned in such manner to create hills and valleys therein; forming a second material layer over said first material layer; etching back the deposited second material layer to produce a surface on the resulting wafer; scanning a predetermined region of the wafer surface with an atomic force microscope; gathering data from the atomic force microscope representing height with respect to position; generating from the gathered data at least one signal indicative of surface roughness using a predetermined procedure; comparing the at least one signal indicative of surface roughness with predefined criteria; when the at least one signal is below a first predetermined threshold of the predetermined criteria, continuing with the integrated circuit fabrication process; when the at least one signal is within an intermediate range of said first predetermined threshold and a second predetermined threshold of the predetermined criteria, performing a remedial process on the wafer; and when the at least one signal is above said second predetermined threshold of the predetermined criteria, discarding the wafer.
Claim 20
Dependent Claim
23 words
The method of claim 16, wherein: said predetermined procedure is an arithmetic mean of the deviations in height from the profile mean procedure.
Claim 21
Dependent Claim
13 words
The method of claim 16, wherein: said predetermined procedure is a root-mean-square procedure.
Claim 22
Dependent Claim
33 words
The method of claim 16, further including the step of: when the at least one signal is above a predetermined threshold, modifying the fabrication process to increase the quality of subsequent wafer production.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |