Dual source gas methods for forming integrated circuit capacitor electrodes

Claim 1

A method for forming an integrated circuit memory device, said method comprising the steps of: forming a memory cell access transistor on an integrated circuit substrate wherein said memory cell access transistor comprises doped source/drain regions of said substrate; forming an insulating layer on said integrated circuit substrate and on said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of one of said doped source/drain regions of said substrate; forming a first amorphous silicon layer on said insulating layer opposite said substrate using a first source gas comprising silane wherein said first amorphous silicon layer fills said contact hole and contacts said exposed source/drain region; forming a second amorphous silicon layer on said first amorphous silicon layer using a second source gas different from said first source gas wherein said second source gas comprises disilane; and patterning said first and second amorphous silicon layers to provide a storage electrode comprising said first and second patterned amorphous silicon layers connected to said exposed source/drain region through said contact hole; forming a dielectric layer on said exposed portions of said storage electrode; and forming a conductive layer on said dielectric layer opposite said storage electrode; wherein said step of forming said dielectric layer is preceded by the step of: forming hemispherical grain polysilicon on exposed portions of said storage electrode made up of said first and second patterned amorphous silicon layers.

Claim 2

A method for forming an integrated circuit memory device, said method comprising the steps of: forming a memory cell access transistor on an integrated circuit substrate wherein said memory cell access transistor comprises doped source/drain regions of said substrate; forming an insulating layer on said integrated circuit substrate and on said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of one of said doped source/drain regions of said substrate; forming a first amorphous silicon layer on said insulating layer opposite said substrate using a first source gas comprising silane wherein said first amorphous silicon layer fills said contact hole and contacts said exposed source/drain region; forming a second amorphous silicon layer on said first amorphous silicon layer using a second source gas different from said first source gas wherein said second source gas comprises disilane; and patterning said first and second amorphous silicon layers to provide a storage electrode comprising said first and second patterned amorphous silicon layers connected to said exposed source/drain region through said contact hole; forming a dielectric layer on said exposed portions of said storage electrode; and forming a conductive layer on said dielectric layer opposite said storage electrode; wherein said step of forming said dielectric layer is preceded by the step of: forming hemispherical grain polysilicon on exposed portions of said storage electrode made up of said first and second patterned amorphous silicon layers.

Claim 13

A method for forming an integrated circuit memory device, said method comprising the steps of: forming a memory cell access transistor on an integrated circuit substrate wherein said memory cell access transistor comprises doped source/drain regions of said substrate; forming an insulating layer on said integrated circuit substrate and on said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of one of said doped source/drain regions of said substrate; forming an amorphous silicon layer on said integrated circuit substrate using a source gas including a mixture of silane and disilane wherein said silicon layer fills said contact hole; patterning said amorphous silicon layer to provide a storage electrode comprising said patterned amorphous silicon layer connected to said exposed source/drain region through said contact hole; forming a dielectric layer on said exposed portions of said storage electrode; and forming a conductive layer on said dielectric layer opposite said storage electrode; wherein said step of forming said dielectric layer is preceded by the step of forming hemispherical grain polysilicon on exposed portions of said storage electrode.

Claim 14

A method for forming an integrated circuit memory device, said method comprising the steps of: forming a memory cell access transistor on an integrated circuit substrate wherein said memory cell access transistor comprises doped source/drain regions of said substrate; forming an insulating layer on said integrated circuit substrate and on said memory cell access transistor wherein said insulating layer has a contact hole therein exposing a portion of one of said doped source/drain regions of said substrate; forming an amorphous silicon layer on said integrated circuit substrate using a source gas including a mixture of silane and disilane wherein said silicon layer fills said contact hole; patterning said amorphous silicon layer to provide a storage electrode comprising said patterned amorphous silicon layer connected to said exposed source/drain region through said contact hole; forming a dielectric layer on said exposed portions of said storage electrode; and forming a conductive layer on said dielectric layer opposite said storage electrode; wherein said step of forming said dielectric layer is preceded by the step of forming hemispherical grain polysilicon on exposed portions of said storage electrode.