US5846871A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit fabrication
Assignee: Nokia of America Corp
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Filing: 1997-08-26
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Granted: 1998-12-08
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Expires: 2017-08-26
Abstract
Abstract Undesirable counter doping of n + /p + gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.
Inventors
- 👤 Jean Ling Lee
- 👤 Yi Ma
- 👤 Sailesh Mansinh Merchant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:20
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D84/0177; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
94 words
A method of integrated circuit fabrication comprising: forming a blanket layer of polysilicon overlying a substrate, said layer of polysilicon having an n + portion and a p + portion; forming a layer of titanium contacting said layer of polysilicon; forming a layer of titanium nitride contacting said layer of titanium; and forming a layer of a refractory metal silicide contacting said layer of titanium nitride; patterning said layer of refractory metal silicide and said layer of titanium nitride and said layer of titanium and said layer of polysilicon to form a gate stack.
Claim 2
Independent Claim
94 words
A method of integrated circuit fabrication comprising: forming a blanket layer of polysilicon overlying a substrate, said layer of polysilicon having an n + portion and a p + portion; forming a layer of titanium contacting said layer of polysilicon; forming a layer of titanium nitride contacting said layer of titanium; and forming a layer of a refractory metal silicide contacting said layer of titanium nitride; patterning said layer of refractory metal silicide and said layer of titanium nitride and said layer of titanium and said layer of polysilicon to form a gate stack.
Claim 3
Independent Claim
93 words
A method of integrated circuit fabrication comprising: forming a blanket layer of polysilicon overlying a substrate, said layer of polysilicon having an n + portion and a p + portion; forming a layer of tungsten contacting said layer of polysilicon; forming a layer of titanium nitride contacting said layer of tungsten; forming a layer of a refractory metal silicide contacting said layer of titanium nitride; patterning said layer of refractory metal silicide and said layer of titanium nitride and said layer of tungsten and said layer of polysilicon to form a gate stack.
Claim 4
Independent Claim
93 words
A method of integrated circuit fabrication comprising: forming a blanket layer of polysilicon overlying a substrate, said layer of polysilicon having an n + portion and a p + portion; forming a layer of tungsten contacting said layer of polysilicon; forming a layer of titanium nitride contacting said layer of tungsten; forming a layer of a refractory metal silicide contacting said layer of titanium nitride; patterning said layer of refractory metal silicide and said layer of titanium nitride and said layer of tungsten and said layer of polysilicon to form a gate stack.
Claim 5
Independent Claim
94 words
A method of integrated circuit fabrication comprising: forming a blanket layer of polysilicon overlying a substrate, said layer of polysilicon having an n + portion and a p + portion; forming a layer of tantalum contacting said layer of polysilicon; forming a layer of titanium nitride contacting said layer of tantalum; and forming a layer of a refractory metal silicide contacting said layer of titanium nitride; patterning said layer of refractory metal silicide and said layer of titanium nitride and said layer of tantalum and said layer of polysilicon to form a gate stack.
Claim 6
Independent Claim
94 words
A method of integrated circuit fabrication comprising: forming a blanket layer of polysilicon overlying a substrate, said layer of polysilicon having an n + portion and a p + portion; forming a layer of tantalum contacting said layer of polysilicon; forming a layer of titanium nitride contacting said layer of tantalum; and forming a layer of a refractory metal silicide contacting said layer of titanium nitride; patterning said layer of refractory metal silicide and said layer of titanium nitride and said layer of tantalum and said layer of polysilicon to form a gate stack.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |