US5064775A
Expired / Lapsed
US
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Method of fabricating an improved polycrystalline silicon thin film transistor
Assignee: Industrial Technology Research Institute
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Filing: 1990-09-04
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Granted: 1991-11-12
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Expires: 2010-09-04
Abstract
Abstract A process of fabricating an improved transistor on a polycrystalline silicon layer, wherein N and P type dopants, in approximate equal concentrations, are introduced into the layer, and the layer heated. The resultant modified polycrystalline silicon layer inhibits the migration of dopants, used to form the active regions of the device, during subsequent heating steps. An improved field effect transistor having a source region, a drain region, and channel region in a polycrystalline silicon layer, the improvement being that the polycrystalline silicon layer has approximately equal concentrations of N and P type dopants embodied therein, which serves to restrain movement of P/N junctions.
Inventors
- 👤 Kun-Zen Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10P; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/15; Y10S428/00; Y10S428/901; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24926; Y10T428/26; Y10T428/263; Y10T428/264; Y10T428/265
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
104 words
A process of fabricating a field effect transistor on a polycrystalline silicon layer, the resultant transistor characterized in that the dopants forming the source and drain are restrained during processing from diffusing, thereby establishing a more stable channel width, comprising: (a) forming a polycrystalline silicon layer of a first thickness on an insulating substrate, (b) implanting both N and P type dopants into said polycrystalline silicon layer in approximately equal concentrations, (c) forming an insulating layer over the resultant modified polycrystalline layer, (d) forming a gate electrode over the polycrystalline silicon layer, (e) and forming source and drain regions in the polycrystalline silicon layer.
Claim 2
Dependent Claim
104 words
A process of fabricating a field effect transistor on a polycrystalline silicon layer, the resultant transistor characterized in that the dopants forming the source and drain are restrained during processing from diffusing, thereby establishing a more stable channel width, comprising: (a) forming a polycrystalline silicon layer of a first thickness on an insulating substrate, (b) implanting both N and P type dopants into said polycrystalline silicon layer in approximately equal concentrations, (c) forming an insulating layer over the resultant modified polycrystalline layer, (d) forming a gate electrode over the polycrystalline silicon layer, (e) and forming source and drain regions in the polycrystalline silicon layer.
Claim 3
Dependent Claim
35 words
The process of claim 1 wherein the concentrations of each of the P and N type dopants in the polycrystalline silicon layer is in the range of 1×10 16 to 1×10 20 cm -3 .
Claim 4
Dependent Claim
18 words
The process of claim 2 wherein the N and P type implanted dopants are phosphorous and boron, respectively.
Claim 5
Dependent Claim
27 words
The process of claim 3 wherein the concentrations of implanted phosphorous and boron are each in the range of 5×10 18 to 5×10 19 cm -3 .
Claim 6
Dependent Claim
71 words
The process of claim 3 wherein the polycrystalline silicon layer is annealed, following the implantation, by heating to a temperature in the range of 600° to 1000° C. for a time in the range of 10 to 60 minutes, the annealing done in an atmosphere of a gas selected from the group consisting of nitrogen or oxygen or mixtures thereof at a pressure in the range of one to five atmospheres.
Claim 7
Dependent Claim
33 words
The process of claim 4 wherein the polycrystalline silicon layer has a thickness in the range of 500 to 5000 Angstroms with a grain size in the range of 0.05 to 1.0 micrometers.
Claim 8
Dependent Claim
41 words
The process of claim 4 wherein the insulating substrate in selected from the group consisting of: (a) a monocrystalline silicon substrate with a silicon dioxide surface layer, (b) a quartz glass substrate, (c) a saphire substrate, and (d) a ceramic substrate.
Claim 9
Dependent Claim
14 words
The process of claim 4 wherein said gate electrode is formed of polycrystalline silicon.
Claim 10
Dependent Claim
24 words
The process of claim 4 wherein the polycrystalline silicon layer has grains with an average diameter in the range of 0.05 to 1.0 micrometers.
Claim 11
Dependent Claim
45 words
The process of claim 4 wherein the polycrystalline silicon layer is re-crystallized following the implantation of phosphorous and boron by heating the device to a temperature in the range of 600° to 1000° C. for a time in the range of 10 to 60 minutes.
Claim 12
Dependent Claim
45 words
The process of claim 4 wherein the polycrystalline silicon layer is re-crystallized following the implantation of phosphorous and boron by heating the device to a temperature in the range of 900° to 1000° C. for a time in the range of 10 to 30 minutes.
Claim 13
Dependent Claim
26 words
The process of claim 11 wherein the recrystallization is achieved in an atmosphere of nitrogen at a pressure in the range of one to five atmospheres.
Claim 14
Dependent Claim
12 words
The process of claim 4 wherein the polycrystalline silicon layer is hydrogenated.
Claim 15
Dependent Claim
35 words
The process of claim 13 wherein the hydrogenation of the polycrystalline silicon layer is achieved by heating the device, following implantation of phosphorous and boron dopants in a low pressure plasma environment that includes hydrogen.
Claim 16
Dependent Claim
41 words
The process of claim 14 wherein the hydrogenation was carried out in parallel plate plasma deposition system, where the plasma is exited to approximately 300 K Hz in a 50% nitrogen and hydrogen atmosphere at a pressure of approximately 400 torr.
Claim 17
Dependent Claim
42 words
The process of claim 10 wherein the polycrystalline silicon layer is hyrogenated in parallel plate plasma deposition system, where the plasma is exited to approximately 300 K Hz in a 50% nitrogen and hydrogen atmosphere at a pressure of approximately 400 torr.
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