US5838176A Expired / Lapsed US ⏱️ 0.0 years remaining

Correlated double sampling circuit

Assignee: Foveon Inc

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Filing: 1997-06-02

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Granted: 1998-11-17

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Expires: 2017-06-02

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Abstract

Abstract A correlated double sampling circuit comprising an input node comprising a first plate of input capacitor and an output node. A first plate of a feedback capacitor is connected to the output node and a second plate of the feedback capacitor is connected to a second plate of the input capacitor. An input transistor has a gate connected to the second plate of the input capacitor, a source connected to a first supply voltage rail, and a drain connected to the output node. A load transistor has a gate connected to a bias node, a drain connected to the output node, and a source connected to a second supply voltage rail. A reset transistor is connected between output node and the second plate of the input capacitor, and has a gate connected to a reset signal line.

Inventors

👤 Tobias Delbruck
👤 Carver A. Mead

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-11-08 05:37

CPC Classifications

G; G11; G11C; G11C7/00; G11C7/06; G11C7/067; G11C27/00; G11C27/02; G11C27/024

Claims Analysis

Total Claims: 2

Claim 1

Independent Claim 130 words

A correlated double sampling circuit comprising: an input node comprising a first plate of input capacitor; an output node; a feedback capacitor having a first plate connected to said output node and a second plate connected to a second plate of said input capacitor; an input transistor having a gate connected to said second plate of said input capacitor, a source connected to a first supply voltage rail, and a drain connected to said output node; a load transistor having a gate connected to a bias node, a drain connected to said output node, and a source connected to a second supply voltage rail; and a reset transistor connected between output node and said second plate of the input capacitor, and having a gate connected to a reset signal line.

Claim 2

Dependent Claim 130 words

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USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-11-16	2002-05-18	2002-11-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-11-16	2006-05-18	2006-11-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-11-16	2010-05-18	2010-11-17	$7700.00	Window Closed / Lapsed

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