Matrix array image sensor chip

Claim 2

An integrated circuit for use as an image array sensor and providing an output signal to an off-circuit read device, said integrated circuit comprising, a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode, horizontal scan means coupled to each cell in the array for scanning each cell row of the array of sensing cells, vertical scan means coupled to each cell in the array for scanning each cell column of said array of sensing cells, a plurality of analogue switch means each connected between at least one of said cell columns and the horizontal scan means for receiving image data from said cells, each of said analogue switch means being also connected by a common conductor to an output amplifier forming the output of the integrated circuit, each of said plurality of analogue switch means includes voltage storage means and first charge sensing amplifier means which provides a preliminary detection of charge created on each cell in response to radiation impinging thereon by converting the detected charge to a voltage using a first charge integrating circuit and capacitively storing the voltage in said voltage storage means, in the form of a charge corresponding to the cell charge, and that said output amplifier comprises a second charge sensing amplifier means which is selectively coupled to said voltage storage means of said analogue switch means, for providing an output signal to the off-circuit read device, said output signal being a voltage proportional to the charge in said voltage storage means.

Claim 3

An integrated circuit as claimed in claim 1 further characterized in that the sensing cell being "read" is reset using a signal from the vertical scan means and signals generated off-circuit of the array whilst said sensing cell is isolated from the signal stored in the voltage storage means.

Claim 4

An integrated circuit as claimed in claim 1 wherein the second charge sensing amplifier means is a second charge integrating circuit.

Claim 5

An integrated circuit as claimed in claim 1 wherein the first charge integrating circuit comprises an inverter consisting of two transistors arranged to provide negative gain and at least one capacitor located between input and output terminals of the inverter to provide charge integration via negative feedback to provide a voltage at the output of the invertor.

Claim 6

An integrated circuit as claimed in claim 1 wherein the first charge integrating circuit comprises an inverter consisting of, one transistor and one resistor, or an operational amplifier arranged to provide negative gain and at least one capacitor located between input and output terminals of the inverter to provide charge integration via negative feedback to provide a voltage at the output of the inverter.

Claim 7

An integrated circuit as claimed in claim 1 wherein the integrated circuit is fabricated using a technology selected from the group consisting of CMOS, PMOS, NMOS, Bipolar, BiMOS, BiCMOS and amorphous silicon technologies.

Claim 8

A camera having an electronic image capture means which includes a two-dimensional matrix array sensor, wherein said matrix array sensor comprises an integrated circuit according to claim 1.

Claim 11

A method as claimed in claim 8 further including the steps following said storing step of isolating the cell from the capacitively stored voltage using a switch which is actuated in response to off-circuit signals; followed by, reseting the cell by a combination of signals from the horizontal scan means and off-circuit signals.

Claim 12

An integrated circuit according to claim 1 wherein said integrated circuit is implemented using a technology selected from CMOS, PMOS, NMOS, Bipolar, BiMOS and BiCMOS technologies.

Claim 13

An integrated circuit according to claim 10 wherein said integrated circuit is implemented using a technology selected from CMOS and BiCMOS technologies.

Claim 14

An integrated circuit according to claim 10 wherein said two-dimensional matrix array of sensing cells has a small cell pitch of less than about 20 microns.

Claim 15

An integrated circuit according to claim 1 wherein each of said plurality of analogue switch means is connected to only one of said cell columns.

Claim 16

An integrated circuit according to claim 13 wherein each of said plurality of analogue switch means is located adjacent its associated cell column.

Claim 17

An integrated circuit according to claim 1 wherein said first charge sensing amplifier includes an inverter.

Claim 18

An integrated circuit according to claim 1 wherein said first charge integrating circuit comprises an inverter means for generating a voltage to balance said charge created on each cell.

Claim 19

An integrated circuit according to claim 1 wherein said first charge integrating circuit includes two transistors.

Claim 20

An integrated circuit according to claim 1 further including a plurality of switches, each of said switches connecting at least on of said voltage storage means to said output amplifier.

Claim 21

An integrated circuit image array sensor comprising: a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each of said sensing cells in said two-dimensional matrix array having a photodiode and a transistor for reading from and writing to the photodiode, each of said sensing cells in said two-dimensional matrix array generating a charge in response to radiation impinging on said cell to provide image data; horizontal scan means coupled to each cell in said two-dimensional matrix array for scanning each cell row of the array of sensing cells; vertical scan means coupled to each cell in said two-dimensional matrix array for scanning each cell column of said array of sensing cells; a plurality of analogue switch means each connected between at least one of said cell columns and said horizontal scan means for receiving said image data from said cells, each of said analogue switch means including charge sensing amplifier means for converting said charge to a voltage by integrating said charge and further including a voltage storage means for capacitively storing said voltage; and an output amplifier which is selectively connected to each of said voltage storage means.

Claim 22

An integrated circuit image array sensor comprising: a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each of said sensing cells in said two-dimensional matrix array having a photodiode and a transistor for reading from and writing to the photodiode, each of said sensing cells in said two-dimensional matrix array generating a charge in response to radiation impinging on said cell to provide image data; horizontal scan means coupled to each cell in said two-dimensional matrix array for scanning each cell row of the array of sensing cells; vertical scan means coupled to each cell in said two-dimensional matrix array for scanning each cell column of said array of sensing cells; a plurality of analogue switch means each connected between at least one of said cell columns and said horizontal scan means for receiving said image data from said cells, each of said analogue switch means including charge sensing amplifier means for converting said charge to a voltage by integrating said charge and further including a voltage storage means for capacitively storing said voltage; and an output amplifier which is selectively connected to each of said voltage storage means.

Claim 23

An integrated circuit for use as an image array sensor and providing an output signal to an off-circuit read device, said integrated circuit comprising, a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode, horizontal scan means coupled to each cell in the array for scanning each cell row of the array of sensing cells, vertical scan means coupled to each cell in the array for scanning each cell column of said array of sensing cells, a plurality of analogue switch means each connected between at least one of said cell columns and the horizontal scan means for receiving image data from said cells, each of said analogue switch means being also connected by a common conductor to a output amplifier forming the output of the integrated circuit, each of said plurality of analogue switch means includes voltage storage means and first charge sensing amplifier means which provides a preliminary detection of charge created on each cell in response to radiation impinging thereon by converting the detected charge to a voltage using a first charge integrating circuit, said first charge integrating circuit comprising an inverter means for generating a voltage to balance said charge created on each cell, and capacitively storing the voltage in said voltage storage means, in the form of a charge corresponding to the cell charge, and that said output amplifier comprises a second charge sensing amplifier means which is selectively coupled to said voltage storage means of said analogue switch means, for providing an output signal to the off-circuit read device, said output signal being a voltage proportional to the charge in said voltage storage means.

Claim 24

An integrated circuit for use as an image array sensor and providing an output signal to an off-circuit read device, said integrated circuit comprising, a two-dimensional matrix array of sensing cells having a plurality of cell columns and a plurality of cell rows, each sensing cell having a photodiode and a transistor for reading from and writing to the photodiode, horizontal scan means coupled to each cell in the array for scanning each cell row of the array of sensing cells, vertical scan means coupled to each cell in the array for scanning each cell column of said array of sensing cells, a plurality of analogue switch means each connected between at least one of said cell columns and the horizontal scan means for receiving image data from said cells, each of said analogue switch means being also connected by a common conductor to a output amplifier forming the output of the integrated circuit, each of said plurality of analogue switch means includes voltage storage means and first charge sensing amplifier means which provides a preliminary detection of charge created on each cell in response to radiation impinging thereon by converting the detected charge to a voltage using a first charge integrating circuit, said first charge integrating circuit comprising an inverter means for generating a voltage to balance said charge created on each cell, and capacitively storing the voltage in said voltage storage means, in the form of a charge corresponding to the cell charge, and that said output amplifier comprises a second charge sensing amplifier means which is selectively coupled to said voltage storage means of said analogue switch means, for providing an output signal to the off-circuit read device, said output signal being a voltage proportional to the charge in said voltage storage means.