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US5835748A
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Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file
Assignee: Intel Corp
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Filing: 1995-12-19
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Granted: 1998-11-10
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Expires: 2015-12-19
Abstract
Abstract A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.
Inventors
- 👤 Doron Orenstein
- 👤 Ofri Wechsler
- 👤 Millind Mittal
- 👤 Andrew F. Glew
- 👤 Larry M. Mennemeier
- 👤 Alexander D. Peleg
- 👤 David Bistry
- 👤 Carole Dulong
- 👤 Eiichi Kowashi
- 👤 Benny Eitan
- 👤 Derrick Lin
- 👤 Ramamohan R. Vakkalagadda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:52
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30014; G06F9/30036; G06F9/30038; G06F9/30098; G06F9/30105; G06F9/30109; G06F9/3012; G06F9/3013; G06F9/30134; G06F9/30181; G06F9/30192; G06F9/38; G06F9/3861
Claims Analysis
Total Claims: 173
Claim 1
Independent Claim
145 words
A processor comprising: a first physical register file for executing scalar instructions; a second physical register file for executing packed data instructions; a transition unit configured to cause said first physical register file and said second physical register file to logically appear to software executing on said processor as a single logical register file; a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack, said stack reference unit including a set of tags, each tags of said set of tags corresponding to a different register in said first physical register file and identifying whether said corresponding register is in either a empty state or a non-empty state; and an fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file.
Claim 2
Dependent Claim
145 words
A processor comprising: a first physical register file for executing scalar instructions; a second physical register file for executing packed data instructions; a transition unit configured to cause said first physical register file and said second physical register file to logically appear to software executing on said processor as a single logical register file; a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack, said stack reference unit including a set of tags, each tags of said set of tags corresponding to a different register in said first physical register file and identifying whether said corresponding register is in either a empty state or a non-empty state; and an fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file.
Claim 3
Dependent Claim
54 words
The processor of claim 1, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said empty state sometime in an interval of time between the start of executing a set of packed data instructions to the start of executing a set of scalar instructions.
Claim 4
Dependent Claim
68 words
The processor of claim 2, wherein: said stack reference unit includes a register in which a top of stack indication can be stored, said top of stack indication identifying one register in said first physical register file as a current top of stack register; and said transition unit is also configured to alter said top of stack indication to an initialization value sometime in said interval of time.
Claim 5
Dependent Claim
91 words
The processor of claim 1, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said non-empty state sometime in a first interval of time between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of packed data instructions and before the execution of said set of scalar instructions.
Claim 6
Dependent Claim
33 words
The processor of claim 4, wherein said set of transition instructions includes a single instruction that causes said transition unit to alter each tag in said set of tags to said empty state.
Claim 7
Dependent Claim
102 words
The processor of claim 1, wherein: each register in said first physical register file corresponds to a different register in said second physical register file; and said transition unit is also configured to store, sometime between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions, a value indicating either not a number or infinity in a sign and exponent field of each register in said first physical register file whose corresponding register in said second physical register file was written to during the execution of said set of packed data instructions.
Claim 8
Dependent Claim
26 words
The processor of claim 1, wherein said first and second physical register files each contain n registers, and said single logical register file contains n registers.
Claim 9
Dependent Claim
22 words
The processor of claim 1, wherein said second physical register file is at least partially aliased on said first physical register file.
Claim 10
Dependent Claim
18 words
The processor of claim 1, wherein said scalar instructions cause said processor to perform scalar floating point operations.
Claim 11
Dependent Claim
17 words
The processor of claim 1, wherein said scalar instructions cause said processor to perform scalar integer operations.
Claim 12
Dependent Claim
19 words
The processor of claim 1, wherein said packed data instructions cause said processor to perform packed floating point operations.
Claim 13
Dependent Claim
18 words
The processor of claim 1, wherein said packed data instructions cause said processor to perform packed integer operations.
Claim 14
Dependent Claim
133 words
A processor comprising: a first physical register file; a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack; a second physical register file; a fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file a transition unit configured to cause said first and second physical register file to logically appear to software executing on said processor as a single logical register file; and a set of tags coupled to said stack reference unit, each tag of said set of tags corresponding to a different register in said single logical register file and identifying whether said corresponding register is in either a empty state or a non-empty state.
Claim 15
Dependent Claim
133 words
A processor comprising: a first physical register file; a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack; a second physical register file; a fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file a transition unit configured to cause said first and second physical register file to logically appear to software executing on said processor as a single logical register file; and a set of tags coupled to said stack reference unit, each tag of said set of tags corresponding to a different register in said single logical register file and identifying whether said corresponding register is in either a empty state or a non-empty state.
Claim 16
Dependent Claim
23 words
The processor of claim 13, wherein said processor is configured to store a plurality of data types in said single logical register file.
Claim 17
Dependent Claim
25 words
The processor of claim 14, wherein said plurality of data types includes at least one scalar data type and at least one packed data type.
Claim 18
Dependent Claim
26 words
The processor of claim 14, wherein said plurality of data types includes at least one floating point data type and at least one integer data type.
Claim 19
Dependent Claim
18 words
The processor of claim 14, wherein said plurality of data types includes scalar floating point and integer data.
Claim 20
Dependent Claim
15 words
The processor of claim 14, wherein said plurality of data types includes packed floating point.
Claim 21
Dependent Claim
55 words
The processor of claim 13, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said empty state sometime in an interval of time between the start of executing a set of packed data instructions to the start of executing a set of floating point instructions.
Claim 22
Dependent Claim
68 words
The processor of claim 19, wherein: said stack reference unit includes a register in which a top of stack indication can de stored, said top of stack indication identifying one register is said first physical register file as a current top of stack register; and said transition unit is also configures to alter siad top of stack indication to an initialization value sonetime in said interval of time.
Claim 23
Dependent Claim
92 words
The processor of claim 13, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said non-empty sometime in a first interval of time between the start of executing a set of packed data instructions and the start of executing a set of floating point instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of packed data instructions and before the execution of said set of floating point instructions.
Claim 24
Dependent Claim
35 words
The processor of claim 21, wherein said set of transition instructions includes a single packed data instruction that causes said transition unit to alter each tag in said set of tags to said empty state.
Claim 25
Dependent Claim
103 words
The processor of claim 13, wherein: each register in said first physical register file corresponds to a different register in said second physical register file; and said transition unit is also configured to store, sometime between the start of executing a set of packed data instructions and the start of executing a set of floating point instructions, a value indicating either not a number or infinity in a sign and exponent field of each register in said first physical register file whose corresponding register in said second physical register file was written to during the execution of said set of packed data instructions.
Claim 26
Dependent Claim
26 words
The processor of claim 13, wherein said first and second physical register files each contain n registers, and said single logical register file contains n registers.
Claim 27
Dependent Claim
22 words
The processor of claim 13, wherein said second physical register file is at least partially aliased on said first physical register file.
Claim 28
Dependent Claim
137 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers; a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers; and an non-stack reference unit coupled to said second set of physical registers.
Claim 29
Dependent Claim
137 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers; a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers; and an non-stack reference unit coupled to said second set of physical registers.
Claim 30
Dependent Claim
11 words
The processor of claim 26, wherein said transition unit is microcode.
Claim 31
Dependent Claim
34 words
The processor of claim 26, wherein said first set of physical registers and said second set of physical registers logically appear as a single set of logical registers to software executing on said processor.
Claim 32
Dependent Claim
131 words
The processor of claim 26, further comprising: a second storage area, coupled to said execution unit, having stored therein a mode indication identifying either a floating point mode or a integer mode, said transition unit altering said mode indication to identify said floating point mode and copying data from said second set of physical registers into said first set of physical registers in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode, said transition unit altering said mode indication to identify said integer mode and copying data from said first set of physical registers into said second set of physical registers in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode.
Claim 33
Dependent Claim
155 words
The processor of claim 29, further comprising; said second storage area also having stored therein a set of dirty indications in one of a dirty state and a clean state, each dirty indication in said set of dirty indications corresponding to a different register in said second set of physical registers; said execution unit, in response to writing data to a selected register in said second set of physical registers, also altering the dirty indication corresponding to said selected register to said dirty state, and said transition unit, in response to receiving one of a set of floating point instructions while said mode indication identifies said integer mode, also writing a value indicating not a number or infinity in a sign and exponent field of each register in said first set of physical registers that corresponds to a register in said second set of physical registers whose corresponding dirty indication is in said dirty state.
Claim 34
Dependent Claim
124 words
The processor of claim 29, wherein: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein; said transition unit also altering each tag in said set of tags to a non-empty state sometime in a first interval of time between the start of executing said set of integer instructions and the start of executing said set of floating point instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of integer instructions and before the execution of said set of floating point instructions.
Claim 35
Dependent Claim
189 words
The processor of claim 29, further comprising: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein, and a transition indication; said execution unit altering said transition indication to a first state in response to executing a transition instruction of said set of integer instructions, and altering said transition indication to a second state in response to executing one of said set of integer instructions other than said transition instruction; said transition unit also altering each tag of said set of tags to an empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said first state; and said transition unit also altering each tag of said set of tags to a non-empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said second state.
Claim 36
Dependent Claim
40 words
The processor of claim 29 wherein said transition unit also alters said top of stack indication to an initialization value in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode.
Claim 37
Dependent Claim
217 words
The processor of claim 26, further comprising: a second storage area having stored therein a mode indication identifying either a floating point mode or a integer mode, and a speculative indication identifying either a speculative state or a non-speculative state; said transition unit altering said mode indication to identify said integer mode, copying data from said first set of physical registers into said second set of physical registers, and altering said speculative indication to identify said speculative state in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode; said execution unit coupled to receive said mode indication and said speculative indication, said execution unit altering said speculative indication to identify said non-speculative state in response to executing one of said set of integer instructions; said transition unit altering said mode indication to identify said floating point mode in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode; and said transition unit also copying data from said second set of physical registers into said first set of physical registers in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and when said speculative indication identifies said non-speculative state.
Claim 38
Dependent Claim
15 words
The processor of claim 26, wherein said floating point operations are scalar floating point operations.
Claim 39
Dependent Claim
15 words
The processor of claim 26, wherein said floating point operations are packed floating point operations.
Claim 40
Dependent Claim
13 words
The processor of claim 26, wherein said integer operations are scalar integer operations.
Claim 41
Dependent Claim
13 words
The processor of claim 26, wherein said integer operations are packed integer operations.
Claim 42
Dependent Claim
39 words
The processor of claim 38 further comprising: a third set of physical registers; said execution unit coupled to said third set of physical registers to perform scalar integer operations on data stored in said third set of physical registers.
Claim 43
Dependent Claim
118 words
A processor comprising: a first plurality of physical registers for executing scalar instructions; a second plurality of physical registers for executing packed data instructions; and a transition means coupled to said first and second plurality of physical registers for causing said first and second plurality of physical registers to appear to software executing on said processor as a single logical register file, and for causing a value indicating not a number or infinity to be written in a sign and exponent field of said first plurality of physical resisters sometime in an interval of time between the start of executing a set of said packed data instructions and the start of executing a set of said scalar instructions.
Claim 44
Dependent Claim
118 words
A processor comprising: a first plurality of physical registers for executing scalar instructions; a second plurality of physical registers for executing packed data instructions; and a transition means coupled to said first and second plurality of physical registers for causing said first and second plurality of physical registers to appear to software executing on said processor as a single logical register file, and for causing a value indicating not a number or infinity to be written in a sign and exponent field of said first plurality of physical resisters sometime in an interval of time between the start of executing a set of said packed data instructions and the start of executing a set of said scalar instructions.
Claim 45
Dependent Claim
26 words
The processor of claim 40, wherein said transition means at least partially aliases said second plurality of physical registers on said first plurality of physical registers.
Claim 46
Dependent Claim
72 words
The processor of claim 40 further comprising: a first means coupled to said first plurality of physical registers for operating said first plurality of physical registers as a stack when said processor is executing certain ones of said scalar instructions; and an second means coupled to said second plurality of physical registers for operating said second plurality of physical registers when said processor is executing certain ones of said packed data instructions.
Claim 47
Dependent Claim
136 words
The processor of claim 42, wherein: said first means further including a set of tags, each tags of said set of tags corresponding to a different register in said first plurality of physical registers and identifying whether said corresponding register is in either a empty state or a non-empty state; and said transition means is also for causing each tag in said set of tags to be altered to said non-empty state sometime in a first interval of time between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of packed data instructions and before the execution of said set of scalar instructions.
Claim 48
Dependent Claim
38 words
The processor of claim 40, further comprising: a first means for operating said first plurality of physical registers as a stack; and a second means for operating said second plurality of physical registers as a fixed register fie.
Claim 49
Dependent Claim
29 words
The processor of claim 44, wherein said first means includes a control registers for storing a top of stack indication identifying one of said first plurality of physical registers.
Claim 50
Dependent Claim
18 words
The processor of claim 40, wherein said scalar instructions cause said processor to perform scalar floating point operations.
Claim 51
Dependent Claim
17 words
The processor of claim 40, wherein said scalar instructions cause said processor to perform scalar integer operations.
Claim 52
Dependent Claim
19 words
The processor of claim 40, wherein said packed data instructions cause said processor to perform packed floating point operations.
Claim 53
Dependent Claim
18 words
The processor of claim 40 further comprising: a third plurality of physical registers for executing scalar integer instructions.
Claim 54
Dependent Claim
155 words
A processor comprising: a plurality of physical register files; an execution unit coupled to said plurality of physical register files; a decode unit, coupled to said plurality of physical register files and said execution unit, configured to cause said execution unit to execute different ones of a plurality of instructions on different ones of said plurality of physical register files; a transition unit, coupled to said plurality of physical register files, configured to cause said plurality of physical register files to logically appear to software as a single logical register file; a stack reference unit, coupled to a first of said plurality of physical register files, configured to operate said first of said plurality of physical register files as a stack; and a flat register file unit, coupled to a second of said plurality of physical register files, configured to operate said second of said plurality of physical register files as a flat register file.
Claim 55
Dependent Claim
155 words
A processor comprising: a plurality of physical register files; an execution unit coupled to said plurality of physical register files; a decode unit, coupled to said plurality of physical register files and said execution unit, configured to cause said execution unit to execute different ones of a plurality of instructions on different ones of said plurality of physical register files; a transition unit, coupled to said plurality of physical register files, configured to cause said plurality of physical register files to logically appear to software as a single logical register file; a stack reference unit, coupled to a first of said plurality of physical register files, configured to operate said first of said plurality of physical register files as a stack; and a flat register file unit, coupled to a second of said plurality of physical register files, configured to operate said second of said plurality of physical register files as a flat register file.
Claim 56
Dependent Claim
29 words
The processor of claim 50 wherein said execution unit is configured to access data from said first of said plurality of physical register files to perform floating point operations.
Claim 57
Dependent Claim
44 words
The processor of claim 50, wherein a first of said plurality of physical register files is used for executing a set of integer instructions and a second of said plurality of physical register files is used for executing a set of floating point instructions.
Claim 58
Dependent Claim
19 words
The processor of claim 52, wherein said set of integer instructions cause said processor to perform packed integer operations.
Claim 59
Dependent Claim
21 words
The processor of claim 52, wherein said set of floating point instructions cause said processor to perform scalar floating point operations.
Claim 60
Dependent Claim
19 words
The processor of claim 52, wherein said set of integer instructions cause said processor to perform scalar integer operations.
Claim 61
Dependent Claim
21 words
The processor of claim 52, wherein said set of floating point instructions cause said processor to perform packed floating point operations.
Claim 62
Dependent Claim
39 words
The processor of claim 50, wherein a first of said plurality of physical register files is used for executing a scalar instructions and a second of said plurality of physical register files is used for executing packed data instructions.
Claim 63
Dependent Claim
71 words
In a data processing apparatus, a method for executing instructions comprising the steps of: executing a set of scalar instructions on a first physical register file, operating said first physical register file as a stack; executing a set of packed data instructions on a second physical register file; and causing said first physical register file and said second physical register file to appear to software as a single logical register file.
Claim 64
Dependent Claim
71 words
In a data processing apparatus, a method for executing instructions comprising the steps of: executing a set of scalar instructions on a first physical register file, operating said first physical register file as a stack; executing a set of packed data instructions on a second physical register file; and causing said first physical register file and said second physical register file to appear to software as a single logical register file.
Claim 65
Dependent Claim
26 words
The method of claim 58, wherein said step of executing said set of scalar instructions includes the step of performing a plurality of floating point operations.
Claim 66
Dependent Claim
34 words
The method of claim 58, wherein said step of executing said set of packed data instructions includes the step of performing either a plurality of integer operations or a plurality of floating point operations.
Claim 67
Dependent Claim
71 words
The method of claim 58, wherein said step of executing said set of scalar instructions further comprised the steps of: determining if said single logical register file is unavailable due to a partial context switch; if said single logical register file is unavailable, then performing the steps of: executing a routine to store in a memory data stored in said logical register file prior to executing said set of scalar instructions.
Claim 68
Dependent Claim
164 words
In a data processing apparatus, a method for executing instructions comprising the steps of: receiving a first instruction; determining that said first instruction is either a floating point instruction or a packed data instruction; determining if a processor containing a first and second set of physical registers is in either a floating point mode or a packed data mode; if said first instruction is said floating point instruction, then transitioning to said floating point mode if said processor is in said packed data mode, and executing said floating point instruction using said first set of physical registers; otherwise, transitioning to said packed data mode if said processor is in said floating point mode, and executing said packed data instruction using said second set of physical registers that is at least partially aliased on said first set of physical registers such that said first set of physical registers and said second set of physical registers logically appears to software as a single logical register file.
Claim 69
Dependent Claim
164 words
In a data processing apparatus, a method for executing instructions comprising the steps of: receiving a first instruction; determining that said first instruction is either a floating point instruction or a packed data instruction; determining if a processor containing a first and second set of physical registers is in either a floating point mode or a packed data mode; if said first instruction is said floating point instruction, then transitioning to said floating point mode if said processor is in said packed data mode, and executing said floating point instruction using said first set of physical registers; otherwise, transitioning to said packed data mode if said processor is in said floating point mode, and executing said packed data instruction using said second set of physical registers that is at least partially aliased on said first set of physical registers such that said first set of physical registers and said second set of physical registers logically appears to software as a single logical register file.
Claim 70
Dependent Claim
107 words
The method of claim 62, wherein said step of executing said floating point instruction using said first set of physical registers and said step of executing said packed data instruction using said second set of physical registers aliased on said first set of physical registers both further comprise the steps of: determining if said single logical register file is unavailable due to a partial context switch; if said single logical register file is unavailable, then performing the steps of: interrupting execution of said first instruction; executing a second routine to store in a memory data stored in said logical register file; restarting execution of said first instruction.
Claim 71
Dependent Claim
33 words
The method of claim 62, wherein said step of executing said floating point instruction using said first set of physical registers is performed using said first set of physical registers as a stack.
Claim 72
Dependent Claim
68 words
The method of claim 62, wherein said step of transitioning to said floating point mode includes the step of copying data stored in said second set of physical registers into said first set of physical registers, and wherein said step of transitioning to said packed data mode includes the step of copying data stored in said first set of physical registers into said second set of physical registers.
Claim 73
Dependent Claim
28 words
The method of claim 62 wherein said step of transitioning to said floating point mode is performed by microcode and execution is resumed without executing any non-microcode instructions.
Claim 74
Dependent Claim
28 words
The method of claim 62 wherein said step of transitioning to said packed data mode is performed by microcode and execution is resumed without executing any non-microcode instructions.
Claim 75
Dependent Claim
66 words
The method of claim 62, wherein said step of transitioning to said floating point mode further includes the step of: setting a top of stack indication to an initialization value, said data processing apparatus operating said first set of physical registers as a stack and said top of stack indication identifying which of said first set of physical registers is currently on top of said stack.
Claim 76
Dependent Claim
168 words
The method of claim 62, wherein: said step of executing said packed data instruction further includes the steps of: determining if said packed data instruction is a transition instruction; if said packed data instruction is said transition instruction, then altering a last instruction indication to indicate the last packed data instruction executed was said transition instruction; otherwise, then altering said last instruction indication to indicate the last packed data instruction executed was not said transition instruction; and wherein said step of transitioning to said floating point mode further includes the step of: determining whether said last instruction indication indicates the last packed data instruction executed was the transition instruction; if said last instruction indication indicates the last packed data instruction executed was the transition instruction, then altering each of a set of tags to an empty state, each register in said first set of physical registers corresponding to a different one of said set of tags; otherwise, altering each of said set of tags to a non-empty state.
Claim 77
Dependent Claim
217 words
The method of claim 62, wherein: said step of transitioning to said packed data mode further includes the step of: altering each dirty indication in a set of dirty indications to indicate a clean state, each dirty indication in said set of dirty indications corresponding to a different one of said second set of physical registers; and wherein said step of executing said packed data instruction further includes the steps of: determining if execution of said packed data instruction causes data to be written to one or more of said second set of physical registers; and if said packed data instruction causes said processor to write to one or more of said second set of physical registers, then altering, to a dirty state, those of said set of dirty indications that correspond to those registers in said second set of physical registers to which data is written to; wherein said step of transitioning to said floating point mode further includes the step of: identifying a subset of said second set of physical registers, said subset including those of said second set of physical registers whose corresponding dirty indication is in said dirty state as dirty registers; and altering a sign and an exponent field of each register in said subset to indicate not a number of infinity.
Claim 78
Dependent Claim
31 words
The method of claim 62, wherein said first set of physical registers is operated as a stack and said second set of physical registers is operated as a fixed register file.
Claim 79
Dependent Claim
317 words
In a data processing apparatus include a processor, a method for executing floating point and packed instructions comprising the steps of: A) receiving a first instruction from a first routine; B) determining that said first instruction is either one of said floating point instructions or said packed data instructions; C) if said first instruction is one of said packed data instructions, then performing the steps of: C1) determining if said processor is in a packed data mode; C2) if said processor is not in said packed data mode, then transitioning to said packed data mode by performing the steps: a) determining if the last one of said packed data instructions executed was a transition instruction; b) if the last one of said packed data instruction executed was said transition instruction, then altering each of a set of tags to a non-empty state, where each tag in said set of tags corresponds to a different one of a set of physical floating point registers; c) if the last one of said packed data instruction executed was not said transition instruction, then altering each of said set of tags to an empty state; d) copying data stored in said set of physical floating point registers into a set of physical packed data registers; and e) micro restarting said first instruction; C3) otherwise, executing said packed data instruction using said set of physical packed data registers; and D) otherwise, performing the steps of: D1) determining if said processor is in a floating point mode; D2) if said processor is not in said floating point mode, then transitioning to said floating point mode by performing the steps of: a) copying data stored in said set of physical packed data registers into said set of physical floating point registers; and b) micro restarting said first instruction; and D3) otherwise, executing said floating point instruction using said set of physical floating point registers.
Claim 80
Dependent Claim
317 words
In a data processing apparatus include a processor, a method for executing floating point and packed instructions comprising the steps of: A) receiving a first instruction from a first routine; B) determining that said first instruction is either one of said floating point instructions or said packed data instructions; C) if said first instruction is one of said packed data instructions, then performing the steps of: C1) determining if said processor is in a packed data mode; C2) if said processor is not in said packed data mode, then transitioning to said packed data mode by performing the steps: a) determining if the last one of said packed data instructions executed was a transition instruction; b) if the last one of said packed data instruction executed was said transition instruction, then altering each of a set of tags to a non-empty state, where each tag in said set of tags corresponds to a different one of a set of physical floating point registers; c) if the last one of said packed data instruction executed was not said transition instruction, then altering each of said set of tags to an empty state; d) copying data stored in said set of physical floating point registers into a set of physical packed data registers; and e) micro restarting said first instruction; C3) otherwise, executing said packed data instruction using said set of physical packed data registers; and D) otherwise, performing the steps of: D1) determining if said processor is in a floating point mode; D2) if said processor is not in said floating point mode, then transitioning to said floating point mode by performing the steps of: a) copying data stored in said set of physical packed data registers into said set of physical floating point registers; and b) micro restarting said first instruction; and D3) otherwise, executing said floating point instruction using said set of physical floating point registers.
Claim 81
Dependent Claim
40 words
The method of claim 72, wherein said step of executing said first instruction using said set of physical packed data registers further includes the step of altering a transition indication to indicate whether said first instruction was said transition instruction.
Claim 82
Dependent Claim
44 words
The method of claim 72, wherein said set of physical floating point registers is operated as a stack, and wherein said step of transitioning to said floating point mode further includes the step of setting a top of stack indication to an initialization value.
Claim 83
Dependent Claim
96 words
The method of claim 72, wherein each registers in said set of physical packed data registers corresponds to a different register in said set of physical floating point registers, wherein said step of transitioning to said floating point mode further includes the step writing a value representing not a number of infinity in a sign and exponent field of each register in said set of physical floating point registers whose corresponding register in said set of physical packed data registers was written to since the most recent floating point instruction of said first routine was executed.
Claim 84
Dependent Claim
146 words
A processor comprising: a first physical register file for executing scalar instructions; a second physical register file for executing packed data instructions, wherein each register in said first physical register file corresponds to a different register in said second physical register file; and a transition unit configured to cause said first physical register file and said second physical register file to logically appear to software executing on said processor as a single logical register file, and to store, sometime between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions, a value indicating either not a number or infinity in a sign and exponent field of each register in said first physical register file whose corresponding register in said second physical register file was written to during the execution of said set of packed data instructions.
Claim 85
Dependent Claim
146 words
A processor comprising: a first physical register file for executing scalar instructions; a second physical register file for executing packed data instructions, wherein each register in said first physical register file corresponds to a different register in said second physical register file; and a transition unit configured to cause said first physical register file and said second physical register file to logically appear to software executing on said processor as a single logical register file, and to store, sometime between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions, a value indicating either not a number or infinity in a sign and exponent field of each register in said first physical register file whose corresponding register in said second physical register file was written to during the execution of said set of packed data instructions.
Claim 86
Dependent Claim
55 words
The processor of claim 76, further comprising: a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack; and an fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file.
Claim 87
Dependent Claim
50 words
The processor of claim 77, wherein: said stack reference unit further comprises a set of tags, each tags of said set of tags corresponding to a different register in said first physical register file and identifying whether said corresponding register is in either a empty state or a non-empty state.
Claim 88
Dependent Claim
54 words
The processor of claim 78, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said empty state sometime in an interval of time between the start of executing a set of packed data instructions to the start of executing a set of scalar instructions.
Claim 89
Dependent Claim
68 words
The processor of claim 79, wherein: said stack reference unit includes a register in which a top of stack indication can be stored, said top of stack indication identifying one register in said first physical register file as a current top of stack register; and said transition unit is also configured to alter said top of stack indication to an initialization value sometime in said interval of time.
Claim 90
Dependent Claim
91 words
The processor of claim 78, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said non-empty state sometime in a first interval of time between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of packed data instructions and before the execution of said set of scalar instructions.
Claim 91
Dependent Claim
33 words
The processor of claim 81, wherein said set of transition instructions includes a single instruction that causes said transition unit to alter each tag in said set of tags to said empty state.
Claim 92
Dependent Claim
26 words
The processor of claim 76, wherein said first and second physical register files each contain n registers, and said single logical register file contains n registers.
Claim 93
Dependent Claim
22 words
The processor of claim 76, wherein said second physical register file is at least partially aliased on said first physical register file.
Claim 94
Dependent Claim
18 words
The processor of claim 76, wherein said scalar instructions cause said processor to perform scalar floating point operations.
Claim 95
Dependent Claim
17 words
The processor of claim 76, wherein said scalar instructions cause said processor to perform scalar integer operations.
Claim 96
Dependent Claim
19 words
The processor of claim 76, wherein said packed data instructions cause said processor to perform packed floating point operations.
Claim 97
Dependent Claim
117 words
A processor comprising: a first physical register file; a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack; a second physical register file; a fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file; a transition unit configured to cause said first and second physical register file to logically appear to software executing on said processor as a single logical register file, said processor configured to store a plurality of data types in said single logical register file, said plurality of data types including scalar floating point and packed integer data.
Claim 98
Dependent Claim
117 words
A processor comprising: a first physical register file; a stack reference unit, coupled to said first physical register file, configured to operate said first physical register file as a stack; a second physical register file; a fixed register file unit, coupled to said second physical register file, configured to operate said second physical register file as a fixed register file; a transition unit configured to cause said first and second physical register file to logically appear to software executing on said processor as a single logical register file, said processor configured to store a plurality of data types in said single logical register file, said plurality of data types including scalar floating point and packed integer data.
Claim 99
Dependent Claim
50 words
The processor of claim 88, wherein: said stack reference unit further comprises a set of tags, each tags of said set of tags corresponding to a different register in said single logical register file and identifying whether said corresponding register is in either a empty state or a non-empty state.
Claim 100
Dependent Claim
55 words
The processor of claim 89, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said empty state sometime in an interval of time between the start of executing a set of packed data instructions to the start of executing a set of floating point instructions.
Claim 101
Dependent Claim
68 words
The processor of claim 90, wherein: said stack reference unit includes a register in which a top of stack indication can be stored, said top of stack indication identifying one register in said first physical register file as a current top of stack register; and said transition unit is also configured to alter said top of stack indication to an initialization value sometime in said interval of time.
Claim 102
Dependent Claim
92 words
The processor of claim 87, wherein: said transition unit is configured to cause each tag in said set of tags to be altered to said non-empty sometime in a first interval of time between the start of executing a set of packed data instructions and the start of executing a set of floating point instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of packed data instructions and before the execution of said set of floating point instructions.
Claim 103
Dependent Claim
35 words
The processor of claim 92, wherein said set of transition instructions includes a single packed data instruction that causes said transition unit to alter each tag in said set of tags to said empty state.
Claim 104
Dependent Claim
103 words
The processor of claim 88, wherein: each register in said first physical register file corresponds to a different register in said second physical register file; and said transition unit is also configured to store, sometime between the start of executing a set of packed data instructions and the start of executing a set of floating point instructions, a value indicating either not a number or infinity in a sign and exponent field of each register in said first physical register file whose corresponding register in said second physical register file was written to during the execution of said set of packed data instructions.
Claim 105
Dependent Claim
26 words
The processor of claim 88, wherein said first and second physical register files each contain n registers, and said single logical register file contains n registers.
Claim 106
Dependent Claim
22 words
The processor of claim 88, wherein said second physical register file is at least partially aliased on said first physical register file.
Claim 107
Dependent Claim
92 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; and a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers, wherein said transition unit is microcode.
Claim 108
Dependent Claim
92 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; and a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers, wherein said transition unit is microcode.
Claim 109
Dependent Claim
59 words
The processor of claim 97 further comprising: a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers; and an non-stack reference unit coupled to said second set of physical registers.
Claim 110
Dependent Claim
34 words
The processor of claim 97, wherein said first set of physical registers and said second set of physical registers logically appear as a single set of logical registers to software executing on said processor.
Claim 111
Dependent Claim
131 words
The processor of claim 97, further comprising: a second storage area, coupled to said execution unit, having stored therein a mode indication identifying either a floating point mode or a integer mode, said transition unit altering said mode indication to identify said floating point mode and copying data from said second set of physical registers into said first set of physical registers in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode, said transition unit altering said mode indication to identify said integer mode and copying data from said first set of physical registers into said second set of physical registers in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode.
Claim 112
Dependent Claim
155 words
The processor of claim 100, further comprising; said second storage area also having stored therein a set of dirty indications in one of a dirty state and a clean state, each dirty indication in said set of dirty indications corresponding to a different register in said second set of physical registers; said execution unit, in response to writing data to a selected register in said second set of physical registers, also altering the dirty indication corresponding to said selected register to said dirty state, and said transition unit, in response to receiving one of a set of floating point instructions while said mode indication identifies said integer mode, also writing a value indicating not a number or infinity in a sign and exponent field of each register in said first set of physical registers that corresponds to a register in said second set of physical registers whose corresponding dirty indication is in said dirty state.
Claim 113
Dependent Claim
124 words
The processor of claim 100, wherein: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein; said transition unit also altering each tag in said set of tags to a non-empty state sometime in a first interval of time between the start of executing said set of integer instructions and the start of executing said set of floating point instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of integer instructions and before the execution of said set of floating point instructions.
Claim 114
Dependent Claim
189 words
The processor of claim 100, further comprising: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein, and a transition indication; said execution unit altering said transition indication to a first state in response to executing a transition instruction of said set of integer instructions, and altering said transition indication to a second state in response to executing one of said set of integer instructions other than said transition instruction; said transition unit also altering each tag of said set of tags to an empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said first state; and said transition unit also altering each tag of said set of tags to a non-empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said second state.
Claim 115
Dependent Claim
94 words
The processor of claim 100 further comprising: a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers, wherein said transition unit also alters said top of stack indication to an initialization value in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode; and an non-stack reference unit coupled to said second set of physical registers.
Claim 116
Dependent Claim
217 words
The processor of claim 97, further comprising: a second storage area having stored therein a mode indication identifying either a floating point mode or a integer mode, and a speculative indication identifying either a speculative state or a non-speculative state; said transition unit altering said mode indication to identify said integer mode, copying data from said first set of physical registers into said second set of physical registers, and altering said speculative indication to identify said speculative state in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode; said execution unit coupled to receive said mode indication and said speculative indication, said execution unit altering said speculative indication to identify said non-speculative state in response to executing one of said set of integer instructions; said transition unit altering said mode indication to identify said floating point mode in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode; and said transition unit also copying data from said second set of physical registers into said first set of physical registers in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and when said speculative indication identifies said non-speculative state.
Claim 117
Dependent Claim
15 words
The processor of claim 97, wherein said floating point operations are scalar floating point operations.
Claim 118
Dependent Claim
15 words
The processor of claim 97, wherein said floating point operations are packed floating point operations.
Claim 119
Dependent Claim
13 words
The processor of claim 97, wherein said integer operations are scalar integer operations.
Claim 120
Dependent Claim
13 words
The processor of claim 97, wherein said integer operations are packed integer operations.
Claim 121
Dependent Claim
39 words
The processor of claim 109 further comprising: a third set of physical registers; said execution unit coupled to said third set of physical registers to perform scalar integer operations on data stored in said third set of physical registers.
Claim 122
Dependent Claim
210 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers; and a second storage area, coupled to said execution unit, having stored therein a mode indication identifying either a floating point mode or a integer mode, said transition unit altering said mode indication to identify said floating point mode and copying data from said second set of physical registers into said first set of physical registers in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode, said transition unit altering said mode indication to identify said integer mode and copying data from said first set of physical registers into said second set of physical registers in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode.
Claim 123
Dependent Claim
210 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers; and a second storage area, coupled to said execution unit, having stored therein a mode indication identifying either a floating point mode or a integer mode, said transition unit altering said mode indication to identify said floating point mode and copying data from said second set of physical registers into said first set of physical registers in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode, said transition unit altering said mode indication to identify said integer mode and copying data from said first set of physical registers into said second set of physical registers in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode.
Claim 124
Dependent Claim
59 words
The processor of claim 111 further comprising: a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers; and an non-stack reference unit coupled to said second set of physical registers.
Claim 125
Dependent Claim
11 words
The processor of claim 111, wherein said transition unit is microcode.
Claim 126
Dependent Claim
34 words
The processor of claim 111, wherein said first set of physical registers and said second set of physical registers logically appear as a single set of logical registers to software executing on said processor.
Claim 127
Dependent Claim
155 words
The processor of claim 111, further comprising; said second storage area also having stored therein a set of dirty indications in one of a dirty state and a clean state, each dirty indication in said set of dirty indications corresponding to a different register in said second set of physical registers; said execution unit, in response to writing data to a selected register in said second set of physical registers, also altering the dirty indication corresponding to said selected register to said dirty state, and said transition unit, in response to receiving one of a set of floating point instructions while said mode indication identifies said integer mode, also writing a value indicating not a number or infinity in a sign and exponent field of each register in said first set of physical registers that corresponds to a register in said second set of physical registers whose corresponding dirty indication is in said dirty state.
Claim 128
Dependent Claim
124 words
The processor of claim 111, wherein: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein; said transition unit also altering each tag in said set of tags to a non-empty state sometime in a first interval of time between the start of executing said set of integer instructions and the start of executing said set of floating point instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of integer instructions and before the execution of said set of floating point instructions.
Claim 129
Dependent Claim
189 words
The processor of claim 111, further comprising: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein, and a transition indication; said execution unit altering said transition indication to a first state in response to executing a transition instruction of said set of integer instructions, and altering said transition indication to a second state in response to executing one of said set of integer instructions other than said transition instruction; said transition unit also altering each tag of said set of tags to an empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said first state; and said transition unit also altering each tag of said set of tags to a non-empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said second state.
Claim 130
Dependent Claim
94 words
The processor of claim 111 further comprising: a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers, wherein said transition unit also alters said top of stack indication to an initialization value in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode; and an non-stack reference unit coupled to said second set of physical registers.
Claim 131
Dependent Claim
145 words
The processor of claim 111, wherein: said second storage area also has stored therein a speculative indication identifying either a speculative state or a non-speculative state; said transition unit also alters said speculative indication to identify said speculative state in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode; said execution unit is coupled to receive said mode indication and said speculative indication, said execution unit alters said speculative indication to identify said non-speculative state in response to executing one of said set of integer instructions; and said transition unit copies data from said second set of physical registers into said first set of physical registers in response to receiving one of said set of floating point instructions only when said mode indication identifies said integer mode and said speculative indication identifies said non-speculative state.
Claim 132
Dependent Claim
15 words
The processor of claim 111, wherein said floating point operations are scalar floating point operations.
Claim 133
Dependent Claim
15 words
The processor of claim 111, wherein said floating point operations are packed floating point operations.
Claim 134
Dependent Claim
13 words
The processor of claim 111, wherein said integer operations are scalar integer operations.
Claim 135
Dependent Claim
13 words
The processor of claim 111, wherein said integer operations are packed integer operations.
Claim 136
Dependent Claim
39 words
The processor of claim 123 further comprising: a third set of physical registers; said execution unit coupled to said third set of physical registers to perform scalar integer operations on data stored in said third set of physical registers.
Claim 137
Dependent Claim
296 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers; and a second storage area having stored therein a mode indication identifying either a floating point mode or a integer mode, and a speculative indication identifying either a speculative state or a non-speculative state; said transition unit altering said mode indication to identify said integer mode, copying data from said first set of physical registers into said second set of physical registers, and altering said speculative indication to identify said speculative state in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode; said execution unit coupled to receive said mode indication and said speculative indication, said execution unit altering said speculative indication to identify said non-speculative state in response to executing one of said set of integer instructions; said transition unit altering said mode indication to identify said floating point mode in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode; and said transition unit also copying data from said second set of physical registers into said first set of physical registers in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and when said speculative indication identifies said non-speculative state.
Claim 138
Dependent Claim
296 words
A processor comprising: a first set of physical registers; a second set of physical registers; an execution unit coupled to said first set of physical registers to perform floating point operations on data stored in said first set of physical registers, and coupled to said second set of physical registers to perform integer operations on data stored in said second set of physical registers; a transition unit to at least partially alias said first set of physical registers onto said second set of physical registers; and a second storage area having stored therein a mode indication identifying either a floating point mode or a integer mode, and a speculative indication identifying either a speculative state or a non-speculative state; said transition unit altering said mode indication to identify said integer mode, copying data from said first set of physical registers into said second set of physical registers, and altering said speculative indication to identify said speculative state in response to receiving one of a set of integer instructions when said mode indication identifies said floating point mode; said execution unit coupled to receive said mode indication and said speculative indication, said execution unit altering said speculative indication to identify said non-speculative state in response to executing one of said set of integer instructions; said transition unit altering said mode indication to identify said floating point mode in response to receiving one of a set of floating point instructions when said mode indication identifies said integer mode; and said transition unit also copying data from said second set of physical registers into said first set of physical registers in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and when said speculative indication identifies said non-speculative state.
Claim 139
Dependent Claim
59 words
The processor of claim 125 further comprising: a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers; and an non-stack reference unit coupled to said second set of physical registers.
Claim 140
Dependent Claim
11 words
The processor of claim 125, wherein said transition unit is microcode.
Claim 141
Dependent Claim
34 words
The processor of claim 125, wherein said first set of physical registers and said second set of physical registers logically appear as a single set of logical registers to software executing on said processor.
Claim 142
Dependent Claim
17 words
The processor of claim 125 wherein said first and second physical register files each contain n registers.
Claim 143
Dependent Claim
155 words
The processor of claim 125, further comprising; said second storage area also having stored therein a set of dirty indications in one of a dirty state and a clean state, each dirty indication in said set of dirty indications corresponding to a different register in said second set of physical registers; said execution unit, in response to writing data to a selected register in said second set of physical registers, also altering the dirty indication corresponding to said selected register to said dirty state, and said transition unit, in response to receiving one of a set of floating point instructions while said mode indication identifies said integer mode, also writing a value indicating not a number or infinity in a sign and exponent field of each register in said first set of physical registers that corresponds to a register in said second set of physical registers whose corresponding dirty indication is in said dirty state.
Claim 144
Dependent Claim
124 words
The processor of claim 125, wherein: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein; said transition unit also altering each tag in said set of tags to a non-empty state sometime in a first interval of time between the start of executing said set of integer instructions and the start of executing said set of floating point instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of integer instructions and before the execution of said set of floating point instructions.
Claim 145
Dependent Claim
189 words
The processor of claim 125, further comprising: said second storage area also has stored therein a set of tags, each tag in said set of tags corresponding to a different registers in said first set of physical registers and identifying information concerning data stored therein, and a transition indication; said execution unit altering said transition indication to a first state in response to executing a transition instruction of said set of integer instructions, and altering said transition indication to a second state in response to executing one of said set of integer instructions other than said transition instruction; said transition unit also altering each tag of said set of tags to an empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said first state; and said transition unit also altering each tag of said set of tags to a non-empty state in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode and said transition indication is in said second state.
Claim 146
Dependent Claim
94 words
The processor of claim 125 further comprising: a stack reference unit coupled to said first set of physical registers, said stack reference unit including a first storage area having stored therein a top of stack indication identifying one register in said first set of physical registers, wherein said transition unit also alters said top of stack indication to an initialization value in response to receiving one of said set of floating point instructions when said mode indication identifies said integer mode; and an non-stack reference unit coupled to said second set of physical registers.
Claim 147
Dependent Claim
15 words
The processor of claim 125, wherein said floating point operations are scalar floating point operations.
Claim 148
Dependent Claim
15 words
The processor of claim 125, wherein said floating point operations are packed floating point operations.
Claim 149
Dependent Claim
13 words
The processor of claim 125, wherein said integer operations are scalar integer operations.
Claim 150
Dependent Claim
13 words
The processor of claim 125, wherein said integer operations are packed integer operations.
Claim 151
Dependent Claim
39 words
The processor of claim 137 further comprising: a third set of physical registers; said execution unit coupled to said third set of physical registers to perform scalar integer operations on data stored in said third set of physical registers.
Claim 152
Dependent Claim
92 words
A processor comprising: a first plurality of physical registers for executing scalar instructions; a second plurality of physical registers for executing packed data instructions; a transition means coupled to said first and second plurality of physical registers for causing said first and second plurality of physical registers to appear to software executing on said processor as a single logical register file; a first means for operating said first plurality of physical registers as a stack; and a second means for operating said second plurality of physical registers as a fixed register file.
Claim 153
Dependent Claim
92 words
A processor comprising: a first plurality of physical registers for executing scalar instructions; a second plurality of physical registers for executing packed data instructions; a transition means coupled to said first and second plurality of physical registers for causing said first and second plurality of physical registers to appear to software executing on said processor as a single logical register file; a first means for operating said first plurality of physical registers as a stack; and a second means for operating said second plurality of physical registers as a fixed register file.
Claim 154
Dependent Claim
26 words
The processor of claim 139, wherein said transition means at least partially aliases said second plurality of physical registers on said first plurality of physical registers.
Claim 155
Dependent Claim
53 words
The processor of claim 139, wherein: said first means operates said first plurality of physical registers as said stack when said processor is executing certain ones of said scalar instructions; and said second means operates said second plurality of physical registers when said processor is executing certain ones of said packed data instructions.
Claim 156
Dependent Claim
136 words
The processor of claim 139, wherein: said first means further including a set of tags, each tags of said set of tags corresponding to a different register in said first plurality of physical registers and identifying whether said corresponding register is in either a empty state or a non-empty state; and said transition means is also for causing each tag in said set of tags to be altered to said non-empty state sometime in a first interval of time between the start of executing a set of packed data instructions and the start of executing a set of scalar instructions if a set of transition instructions is not executed sometime in a second interval of time after the execution of said set of packed data instructions and before the execution of said set of scalar instructions.
Claim 157
Dependent Claim
29 words
The processor of claim 139, wherein said first means includes a control register for storing a top of stack indication identifying one of said first plurality of physical registers.
Claim 158
Dependent Claim
66 words
The processor of claim 139, wherein: said transition means is also for causing a value indicating not a number or infinity to be written in a sign and exponent field of said first plurality of physical registers sometime in an interval of time between the start of executing a set of said packed data instructions and the start of executing a set of said scalar instructions.
Claim 159
Dependent Claim
18 words
The processor of claim 139, wherein said scalar instructions cause said processor to perform scalar floating point operations.
Claim 160
Dependent Claim
17 words
The processor of claim 139, wherein said scalar instructions cause said processor to perform scalar integer operations.
Claim 161
Dependent Claim
19 words
The processor of claim 139, wherein said packed data instructions cause said processor to perform packed floating point operations.
Claim 162
Dependent Claim
18 words
The processor of claim 139, wherein said packed data instructions cause said processor to perform packed integer operations.
Claim 163
Dependent Claim
18 words
The processor of claim 148 further comprising: a third plurality of physical registers for executing scalar integer instructions.
Claim 164
Dependent Claim
249 words
In a data processing apparatus include a processor, a method for executing floating point and packed instructions comprising the steps of: A) receiving a first instruction from a first routine; B) determining that said first instruction is either one of said floating point instructions or said packed data instructions; C) if said first instruction is one of said packed data instructions, then performing the steps of: C1) determining if said processor is in a packed data mode; C2) if said processor is not in said packed data mode, then transitioning to said packed data mode by performing the steps: a) copying data stored in a set of physical floating point registers into a set of physical packed data registers; and b) micro restarting said first instruction; C3) otherwise, executing said packed data instruction using said set of physical packed data registers; and D) otherwise, performing the steps of: D1) determining if said processor is in a floating point mode; D2) if said processor is not in said floating point mode, then transitioning to said floating point mode by performing the steps of: a) copying data stored in said set of physical packed data registers into said set of physical floating point registers, wherein said set of physical floating point registers is operated as a stack; b) setting a top of stack indication to an initialization value; and c) micro restarting said first instruction; and D3) otherwise, executing said floating point instruction using said set of physical floating point registers.
Claim 165
Dependent Claim
249 words
In a data processing apparatus include a processor, a method for executing floating point and packed instructions comprising the steps of: A) receiving a first instruction from a first routine; B) determining that said first instruction is either one of said floating point instructions or said packed data instructions; C) if said first instruction is one of said packed data instructions, then performing the steps of: C1) determining if said processor is in a packed data mode; C2) if said processor is not in said packed data mode, then transitioning to said packed data mode by performing the steps: a) copying data stored in a set of physical floating point registers into a set of physical packed data registers; and b) micro restarting said first instruction; C3) otherwise, executing said packed data instruction using said set of physical packed data registers; and D) otherwise, performing the steps of: D1) determining if said processor is in a floating point mode; D2) if said processor is not in said floating point mode, then transitioning to said floating point mode by performing the steps of: a) copying data stored in said set of physical packed data registers into said set of physical floating point registers, wherein said set of physical floating point registers is operated as a stack; b) setting a top of stack indication to an initialization value; and c) micro restarting said first instruction; and D3) otherwise, executing said floating point instruction using said set of physical floating point registers.
Claim 166
Dependent Claim
111 words
The method of claim 150, wherein: wherein said step of transitioning to said packed data mode further includes the steps of: determining if the last one of said packed data instructions executed was a transition instruction; if the last one of said packed data instruction executed was said transition instruction, then altering each of a set of tags to a non-empty state, where each tag in said set of tags corresponds to a different one of said set of physical floating point registers; and if the last one of said packed data instruction executed was not said transition instruction, then altering each of said set of tags to an empty state.
Claim 167
Dependent Claim
40 words
The method of claim 151, wherein said step of executing said first instruction using said set of physical packed data registers further includes the step of altering a transition indication to indicate whether said first instruction was said transition instruction.
Claim 168
Dependent Claim
96 words
The method of claim 150, wherein each registers in said set of physical packed data registers corresponds to a different register in said set of physical floating point registers, wherein said step of transitioning to said floating point mode further includes the step writing a value representing not a number of infinity in a sign and exponent field of each register in said set of physical floating point registers whose corresponding register in said set of physical packed data registers was written to since the most recent floating point instruction of said first routine was executed.
Claim 169
Dependent Claim
303 words
In a data processing apparatus include a processor, a method for executing floating point and packed instructions comprising the steps of: A) receiving a first instruction from a first routine; B) determining that said first instruction is either one of said floating point instructions or said packed data instructions; C) if said first instruction is one of said packed data instructions, then performing the steps of: C1) determining if said processor is in a packed data mode; C2) if said processor is not in said packed data mode, then transitioning to said packed data mode by performing the steps: a) copying data stored in a set of physical floating point registers into a set of physical packed data registers; and b) micro restarting said first instruction; C3) otherwise, executing said packed data instruction using said set of physical packed data registers; and D) otherwise, performing the steps of: D1) determining if said processor is in a floating point mode; D2) if said processor is not in said floating point mode, then transitioning to said floating point mode by performing the steps of: a) copying data stored in said set of physical packed data registers into said set of physical floating point registers, wherein each registers in said set of physical packed data registers corresponds to a different register in said set of physical floating point registers, b) writing a value representing not a number of infinity in a sign and exponent field of each register in said set of physical floating point registers whose corresponding register in said set of physical packed data registers was written to since the most recent floating point instruction of said first routine was executed; and c) micro restarting said first instruction; and D3) otherwise, executing said floating point instruction using said set of physical floating point registers.
Claim 170
Dependent Claim
303 words
In a data processing apparatus include a processor, a method for executing floating point and packed instructions comprising the steps of: A) receiving a first instruction from a first routine; B) determining that said first instruction is either one of said floating point instructions or said packed data instructions; C) if said first instruction is one of said packed data instructions, then performing the steps of: C1) determining if said processor is in a packed data mode; C2) if said processor is not in said packed data mode, then transitioning to said packed data mode by performing the steps: a) copying data stored in a set of physical floating point registers into a set of physical packed data registers; and b) micro restarting said first instruction; C3) otherwise, executing said packed data instruction using said set of physical packed data registers; and D) otherwise, performing the steps of: D1) determining if said processor is in a floating point mode; D2) if said processor is not in said floating point mode, then transitioning to said floating point mode by performing the steps of: a) copying data stored in said set of physical packed data registers into said set of physical floating point registers, wherein each registers in said set of physical packed data registers corresponds to a different register in said set of physical floating point registers, b) writing a value representing not a number of infinity in a sign and exponent field of each register in said set of physical floating point registers whose corresponding register in said set of physical packed data registers was written to since the most recent floating point instruction of said first routine was executed; and c) micro restarting said first instruction; and D3) otherwise, executing said floating point instruction using said set of physical floating point registers.
Claim 171
Dependent Claim
111 words
The method of claim 154, wherein: wherein said step of transitioning to said packed data mode further includes the steps of: determining if the last one of said packed data instructions executed was a transition instruction; if the last one of said packed data instruction executed was said transition instruction, then altering each of a set of tags to a non-empty state, where each tag in said set of tags corresponds to a different one of said set of physical floating point registers; and if the last one of said packed data instruction executed was not said transition instruction, then altering each of said set of tags to an empty state.
Claim 172
Dependent Claim
40 words
The method of claim 155, wherein said step of executing said first instruction using said set of physical packed data registers further includes the step of altering a transition indication to indicate whether said first instruction was said transition instruction.
Claim 173
Dependent Claim
44 words
The method of claim 154, wherein said set of physical floating point registers is operated as a stack, and wherein said step of transitioning to said floating point mode further includes the step of setting a top of stack indication to an initialization value.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-11-09 | 2002-05-11 | 2002-11-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-09 | 2006-05-11 | 2006-11-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-11-09 | 2010-05-11 | 2010-11-10 | $7700.00 | Window Closed / Lapsed |