Digital multiplier employing CMOS transistors

Claim 1

A digital multiplier for multiplying a first binary N bit number to a second binary N bit number to obtain a final binary number, comprising: multiplying means for multiplying each bit of the first N bit number by each bit of the second N bit number, and for outputting in parallel partial products indicative of the multiplication, said partial products being one of a binary "1" and "0"; a plurality of 1's counters adjacently aligned from least significance to most significance, each of said 1's counters receiving at least one partial product output from the multiplying means and counting a number of the binary "1"s, each of said 1's counters also outputting one bit of the final binary number and outputting at least one carry bit to the adjacent 1's counter of more significance, each of said 1's counters comprising: a plurality of input lines; a plurality of lines intersecting said input lines at intersections; a plurality of PMOS transistors coupled between said input lines and said lines at ones of said intersections; a plurality of biasing NMOS transistors coupled between said input lines and said lines at other ones of said intersections; a plurality of amplifiers coupled to corresponding ones of said lines, said amplifiers being arranged from least significance to most significance and having respective outputs; and a plurality of feedback NMOS transistors coupled between said lines of said lower significant amplifiers and said outputs of said higher significant amplifiers.