Binary batch adder utilizing threshold counters

Claim 2

A counter for counting a plurality of binary inputs in terms of a fewer number of weighted binary outputs comprising: first and second pluralities of counter input means, each of said inputs being connected to a counter input in only a predetermined one of said first or said second plurality of counter input means; first threshold function generator means consisting of one level of logic circuitry which includes a first group of one or more logic performing circuits and which includes means connectiNg said first plurality of counter inputs to said first group whereby said first group logically combines said first plurality of counter inputs to form a first plurality of binary threshold functions; second threshold function generator means consisting of one level of logic circuitry which includes a second group of one or more logic performing circuits and which includes means connecting said second plurality of counter inputs to said second group whereby said second group logically combines said second plurality of counter inputs to form a second plurality of binary threshold functions; and first, second and third threshold function combining means where each combining means consists of one level of logic circuitry, where each combining means is connected to receive selected different ones of said first and said second plurality of binary threshold functions and whereby said combining means logically combine threshold functions to form first, second and third weighted counter outputs, respectively.

Claim 3

The apparatus of claim 1 wherein said first group and said second group of logic performing circuits include a plurality of current switches for performing logical functions.

Claim 4

The apparatus of claim 1 wherein said first plurality of the counter inputs numbers three and wherein said second plurality of the counter inputs numbers four thereby forming a 7-to-3 counter.

Claim 5

The apparatus of claim 3 wherein said plurality of binary threshold functions consists of (A,B,C) (0), (A,B,C) (1,2,3), (A, B,C) (0,1), (A,B,C) (0,1,2,), (A,B,C) (3) and (A,B,C) (0,1,3); and wherein said second plurality of binary threshold functions consists of (D,E,F,G) (0), (D,E,F,G) (1,2,3,4), (D,E,F,G) (0, 1), (D,E,F,G) (2,3,4), (D,E,F,G) (0,1,2), (D,E,F,G) (0,1,2,3) and (D,E,F,G) (4).

Claim 6

A batch adder apparatus for simultaneously adding a plurality of numbers wherein each number includes a plurality of bit positions comprising: a plurality of n ordered counters, one for each bit position, wherein each counter is connected to receive a counter input from each number so as to count the inputs in terms of a fewer number of counter outputs and wherein each counter includes, first threshold function generator means consisting of one level of logic circuitry which includes a first group of one or more logic performing circuits and which includes means connecting a first plurality of the counter inputs to said first group hereby said first group logically combines said first plurality of the counter inputs to form a first plurality of binary threshold functions; second threshold function generator means consisting of one level of logic circuitry which includes a second group of one or more logic performing circuits and which includes means connecting a second plurality of the counter inputs to said second group whereby said second group logically combines said second plurality of the counter inputs to form a second plurality of binary threshold functions; first, second and third threshold function combining means where each combining means consists of one level of logic circuitry, where each combining means is connected to receive selected different ones of said first and said second plurality of binary threshold functions and whereby said combining means logically combine threshold functions to form a first, a second and a third counter output; and an adder including a plurality of n ordered stages, one stage for each bit position and each stage corresponding to one of said counters, and including, for each ith counter, means connecting said first counter output to the ith adder stage, means connecting said second counter output to the (i+1)th order stage, and means connecting said third counter output to the (i+2)th order stAge whereby said adder forms the final addition of said plurality of numbers.

Claim 7

A batch adder apparatus for simultaneously adding a plurality of numbers wherein each number includes a plurality of bit positions comprising: a plurality of n ordered counters, one for each bit position, wherein each counter is connected to receive a counter input from each number so as to count the inputs in terms of a fewer number of counter outputs and wherein each counter includes, first threshold function generator means consisting of one level of logic circuitry which includes a first group of one or more logic performing circuits and which includes means connecting a first plurality of the counter inputs to said first group hereby said first group logically combines said first plurality of the counter inputs to form a first plurality of binary threshold functions; second threshold function generator means consisting of one level of logic circuitry which includes a second group of one or more logic performing circuits and which includes means connecting a second plurality of the counter inputs to said second group whereby said second group logically combines said second plurality of the counter inputs to form a second plurality of binary threshold functions; first, second and third threshold function combining means where each combining means consists of one level of logic circuitry, where each combining means is connected to receive selected different ones of said first and said second plurality of binary threshold functions and whereby said combining means logically combine threshold functions to form a first, a second and a third counter output; and an adder including a plurality of n ordered stages, one stage for each bit position and each stage corresponding to one of said counters, and including, for each ith counter, means connecting said first counter output to the ith adder stage, means connecting said second counter output to the (i+1)th order stage, and means connecting said third counter output to the (i+2)th order stAge whereby said adder forms the final addition of said plurality of numbers.