Digital multiplier employing matrix of nor circuits

Claim 1

A MULTIPLIER COMPRISING A PLURALITY OF NOR CIRCUITS EACH HAVING TWO INPUT LEADS AND AN OUTPUT LEAD, EACH NOR CIRCUITS BEING OPERABLE TO GENERATE AN OUTPUT SIGNAL ON THE OUTPUT LEAD WHEN NO INPUT SIGNALS APPEAR ON EITHER OF THE INPUT LEADS, AND BEING OPERABLE TO PROVIDE NO SIGNAL ON THE OUTPUT LEAD WHEN AN INPUT APPEARS ON AT LEAST ONE OF THE INPUT LEADS, SAID MULTIPLIER INCLUDING TWO GROUPS OF INPUT TERMINALS FOR RECEIVING TWO RESPECTIVE GROUPS OF BINARY CODED SIGNALS, THE INPUT LEADS OF EACH OF THE NOR CIRCUITS BEING COUPLED RESPECTIVELY TO ONE OF THE INPUT TERMINALS OF EACH GROUP, AND A PLURALITY OF ENCODER ADDER CIRCUITS EACH HAVING A PLULARITY OF INPUT LEADS AND AN OUTPUT LEAD, THE INPUT LEADS OF ENCODER ADDER CIRCUITS BEING COUPLED TO RESPECTIVE ONES OF THE OUTPUT LEADS OF THE NOR CIRCUITS, AND THE OUTPUT LEADS BEING OPERABLE TO GENERATE BINARY SIGNALS CORRESPONDING TO THE PRODUCT OF THE BINARY SIGNALS IMPRESSED UPON THE RESPECTIVE GROUPS OF INPUT TERMINALS, SAID ENCODER ADDER CIRCUITS BEING COUPLED TO EACH OTHER TO PROPAGATE CARRY SIGNALS FROM ONE ENCODER ADDER CIRCUIT TO ANOTHER.