Digital signal processor with parallel multipliers

Claim 2

A digital signal processor dedicated to digital signal processing, comprising a memory portion, a control portion, an arithmetic operation portion and a data bus serving as a data transmission line among said memory portion, said control portion and said arithmetic operation portion, said memory portion comprising data memories for storing data to be multiplied, said control portion comprising: a program memory for storing data, reading means for reading out successively the program data stored in said program memory, and output means for providing various control signals based on said program data read out from said program memory, said arithmetic operation portion comprising: a plurality of multipliers connected directly with said data memories for multiplying data provided from said data memories, an arithmetic and logic unit including a plurality of arithmetic and logic circuits, said arithmetic and logic unit connected directly with said plurlaity of multipliers for applying determined arithmetic and logic operation to outputs of said multipliers, and an accumulator for storing temporarily an output of said arithmetic and logic unit so that said output is supplied to said data bus.

Claim 3

A digital signal processor in accordance with claim 1, wherein said plurality of arithmetic and logic circuits comprise: an arithmetic and logic circuit for addition processing connected directly with said plurality of multipliers so as to add the outputs of said plurality of multipliers, and an arithmetic and logic circuit for accumulation processing connected directly with said arithmetic and logic circuit for addition processing and connected with said accumulator so as to add an output of said arithmetic and logic circuit for addition processing to a value stored in said accumulator.

Claim 4

A digital signal processor in accordance with claim 1, wherein said data memories comprise a plurality of memories.

Claim 5

A digital signal processor in accordance with claim 3, wherein said plurality of memories comprise: a random access memory for storing non-constant data, and a read-only memory for storing constant data.

Claim 6

A digital signal processor dedicated to digital signal processing, comprising a memory portion, a control portion, an arithmetic operation portion and a data bus serving as a data transmission line among said memory portion, said control portion and said arithmetic operation portion, said memory portion comprising data memories for storing data to be multiplied including a random access memory for storing non-constant data, and a read-only memory for storing constant data, said random access memory having a plurality of output ports, and said read-only memory having a number of memory areas capable of reading out data independently, said control portion comprising: a program memory for storing data, reading means for reading out successively the program data stored in said program memory, and output means for providing various control signals based on said program data read out from said program memory, said arithmetic operation portion comprising: a plurality of multipliers, each having an input connected directly with a corresponding output port of said random access memory, for multiplying data provided from said data memories, the number of said memory areas of said read-only memory being equal to a number of said multipliers, an arithmetic and logic unit connected directly with said plurality of multipliers for applying predetermined arithmetic and logic operation to outputs of said multipliers, and an accumulator for storing temporarily an output of said arithmetic and logic unit so that said output is supplied to said data bus.

Claim 7

A digital signal processor dedicated to digital signal processing, comprising a memory portion, a control portion, an arithmetic operation portion and a data bus serving as a data transmission line among said memory portion, said control portion and said arithmetic operation portion, said memory portion comprising data memories for storing data to be multiplied including a random access memory for storing non-constant data, and a read-only memory for storing constant data, said random access memory having a plurality of output ports, and said read-only memory having a number of memory areas capable of reading out data independently, said control portion comprising: a program memory for storing data, reading means for reading out successively the program data stored in said program memory, and output means for providing various control signals based on said program data read out from said program memory, said arithmetic operation portion comprising: a plurality of multipliers, each having an input connected directly with a corresponding output port of said random access memory, for multiplying data provided from said data memories, the number of said memory areas of said read-only memory being equal to a number of said multipliers, an arithmetic and logic unit connected directly with said plurality of multipliers for applying predetermined arithmetic and logic operation to outputs of said multipliers, and an accumulator for storing temporarily an output of said arithmetic and logic unit so that said output is supplied to said data bus.

Claim 8

A digital signal processor dedicated to digital signal processing, comprising a memory portion, a control portion, an arithmetic operation portion and a data bus serving as a data transmission line among said memory portion, said control portion and said arithmetic operation portion, said memory portion comprising data memories for storing data to be multiplied, said control portion comprising: a program memory for storing data, reading means for reading out successively the program data stored in said program memory, and output means for providing various control signals based on said program data read out from said program memory, said arithmetic operation portion comprising: a plurality of multipliers connected directly with said data memories for multiplying data provided from said data memories, wherein said data memories have a sufficiently high access speed compared with a processing speed of said multipliers so that data can be transmitted from said data memories to each of said multipliers in a time-sharing manner, an arithmetic and logic unit connected directly with said plurality of multipliers for applying predetermined arithmetic and logic operation to the outputs of said multipliers, and an accumulator for storing temporarily an output of said arithmetic and logic unit so that said output is supplied to said data bus.

Claim 9

A digital signal processor dedicated to digital signal processing, comprising a memory portion, a control portion, an arithmetic operation portion and a data bus serving as a data transmission line among said memory portion, said control portion and said arithmetic operation portion, said memory portion comprising data memories for storing data to be multiplied, said control portion comprising: a program memory for storing data, reading means for reading out successively the program data stored in said program memory, and output means for providing various control signals based on said program data read out from said program memory, said arithmetic operation portion comprising: a plurality of multipliers connected directly with said data memories for multiplying data provided from said data memories, wherein said data memories have a sufficiently high access speed compared with a processing speed of said multipliers so that data can be transmitted from said data memories to each of said multipliers in a time-sharing manner, an arithmetic and logic unit connected directly with said plurality of multipliers for applying predetermined arithmetic and logic operation to the outputs of said multipliers, and an accumulator for storing temporarily an output of said arithmetic and logic unit so that said output is supplied to said data bus.