Generalized 7/3 counters

Claim 2

A 7/3 counter for generating a three bit output including a sum bit (S), a first carry bit (C 1 ), and a second carry bit (C 2 ), such that C 2 C 1 S represents the difference between the number of positive, active bits and the number of negative, active bits in a seven-bit input including signed input bits x 6 x 5 x 4 x 3 x 2 x 1 x 0 , the counter including: EXCLUSIVE-OR means responsive to the seven-bit input for generating the sum bit according to: S=x.sub.0 Vx.sub.1 Vx.sub.2 Vx.sub.3 Vx.sub.4 Vx.sub.5 Vx.sub.6, where "V" denotes the EXCLUSIVE-OR logical operation; and logic means for combining a group of seven signed input bits to produce C 1 and C 2 , the seven signed input bits having a first bit sign pattern which corresponds to a first range of possible sums of the seven bits or a second bit sign pattern which is the inverse of the first bit sign pattern and which corresponds to a second range of possible sums of the seven bits.

Claim 3

The 7/3 counter of claim 1, wherein the firs range of possible sums is 0 through 7, the second range of possible sums is -7 through 0, and wherein said logic means generate c 1 and c 2 in accordance with the logical relationships: c.sub.1 =4.sup.+.sub.(0:6) '2.sup.+.sub.(0:6) +6.sup.+.sub.(0:6) ; c.sub.2 =4.sup.+.sub.(0:6) ; and wherein the expression Γ + (α:β) means that at least Γ of said seven bits are active over a range α through β of said seven bits and an apostrophe denotes logical inversion.

Claim 4

The 7/3 counter of claim 2 wherein said logic means include a plurality of substage means for generating a plurality of logical constructs, said substrate means including four first substages, two second substates, one third substage and one fourth substage: said first substages receiving said seven bits and generating the constructs 2(0:1), 1 + (0:1);2(2:23), 1 + (2:3); 2(4:5), 1 + (4:5); and x6, x6'; said second substages receiving said first substage constructs and generating the constructs 4(0:3), 3 + (0:3), 2 + (0:3), 1 + (0:3); and 3(4:6), 2 + (4:6), 1 + (4:6); said third substage receiving said second substage constructs and generating the constructs 6 + (0:6), 4 + (0:6)', 2 + (0:6) and 4 + (0:6)=c 2 ; said fourth substage receiving said third substage constructs and generating the value c 1 ; and wherein the expression Γ + (α:β) means that at least Γ of said seven bits are "on" over a range α through β of said seven bits, the expression Γ(α:β) means that exactly Γ of said seven bits are "on" over a range α-β of said seven bits and x i ' means the with bit x i is inverted.

Claim 5

The 7/3 counter of claim 1 wherein the first range of possible sums is -1 through 6, the second range of possible sums is 1 through -6 and wherein said logic means calculate c 1 and c 2 in accordance with the logical relationships; c.sub.1 =1.sup.+.sub.(0:5) 3.sup.+.sub.(0:5 'x.sub.6 +5.sup.+.sub.(0:5) x.sub.6 +2.sup.+.sub.(0:5) 4.sup.+.sub.(0:5) 'x.sub.6 +6.sub.(0:5) x.sub.6 ; c.sub.2 =x.sub.6 3.sup.+.sub.(0:5) +x.sub.6 4.sup.+.sub.(0:5 ; and wherein Γ + (α:β) means that at least Γ of said seven bits are "on" over a range α through β of said seven bits, Γ + (α:β)'means that at least Γ of said seven bits are "off" over a range α through β of said seven bits, Γ(α:β) means that exactly Γ of said seven bits are "on" over a range α through β of said seven bits, and x i means the bit x i is "off".

Claim 6

The 7/3 counter of claim 4 wherein said logic means include a plurality of substage means for generating a plurality of logical constructs, said substage means including three first substages, one second substage and one third substage: said first substages receiving said seven bits and generating the constructs 3(0:2), 2 + (0:2), 1 + (0:2); 3(3:5), 2 + (3:5), 1 + (3:5); and x 6 , x 6 ; said second substage receiving said first stage constructs, except the constructs x 6 and x 6 , and generating the constructs 6(0:5), 5 + (0:5), 4 + (0:5), 3 + (0:5), 2 + (0:5), 1 + (0:5); said third substage receiving said second stage constructs and the constructs x 6 , x 6 , and generating c 1 and c 2 ; and wherein Γ + (α:β) means that at least Γ of said seven bits are "on" over a range α through β of said seven bits, the expression Γ(α:β) means that exactly Γ of said seven bits are "on" over a range α-β of said seven bits and x i means the input x i is inverted.

Claim 7

The 7/3 counter of claim 1 wherein the first range of possible sums is -2 through 5, the second range of possible sums is 2 through -5, and wherein said logic means calculate c 1 and c 2 in accordance with the following logical relationships: c.sub.1 =2.sup.+.sub.(0:4)' 2.sub.(5:6) +0.sub.(0:4) 1.sup.+.sub.(5:6 +2.sup.+.sub.(0:4) 4.sup.+.sub.(0:4) '0.sub.(5:6) +3.sup.+.sub.(0:4) 5.sub.(0:4) '1.sub.(5:6) +4.sup.+.sub.(0:4) 2.sub.(5:6) ; c.sub.2 =2.sup.+.sub.(0:4) 0.sub.(5:6) +3+.sub.(0:4) 1.sub.(5:6) +4+.sub.(0:4) ; and wherein Γ + (α:β) means that at least Γ0 of said seven bits are "on" over a range α through β of said seven bits, Γ + (α:β)' means that at least Γ of said seven bits are "off" over a range α through β of said seven bits, Γ(α:β) means that exactly Γ of said seven bits are "on" over a range α through β of said seven bits.

Claim 8

The 7/3 counter of claim 6 wherein said logic means include a plurality of substage means for generating a plurality of logical constructs, said substage means including three first substages, one second substage and one third substage: said first substages receiving said input digits and generating the constructs 3(0:2), 2 + (0:2), 1 + (0:2), 0(0:2); 2(3:4), 1 + (3:4), 0(3:4); and 2(5:6), 1 + (5:6), 1(5,6), 0(5:6); said second substage receiving said first stage constructs, except the constructs 2(5:6), 1 + (5:6), 1(5:6) and 0(5:6), and generating the constructs 5(0:4), 4 + (0:4), 3 + (0:4), 2 + (0:4), 1 + (0:4) and 0(0:4); said third substage receiving said second stage constructs and said first stage constructs 2(5:6), 1 + (5:6), 1(5:6) and 0(5:6), and generating c 1 and c 2 ; and wherein the expression Γ + (α:β) means that at least Γ of said seven bits are "on" over a range α through β of said seven bits and Γ(α:β) means that exactly Γ of said seven bits are

Claim 9

The 7/3 counter of claim 1 wherein the first range of possible sums is -3 through 4, the second range of possible sums is 3 through -4, and wherein said logic means generate c 1 and c 2 in accordance with the following logical relationships: c.sub.1 =0.sub.(0:3) 2.sup.+.sub.(4:6) +2.sup.+.sub.(0:3) '3.sub.(4:6) +1.sup.+.sub.(0:3) 3.sup.+.sub.(0:3) 0.sub.(4:6) +2.sup.+.sub.(0:3) 4.sub.(0:3) '1.sub.(4:6) +3.sup.+.sub.(0:3) 2.sup.+.sub.(4:6) 3.sub.(4:6) '+4.sub.(0:3) 2.sup.+.sub.(4:6) c.sub.2 =1.sup.+.sub.(0:3) 1.sup.+.sub.(4:6) '+2.sup.+.sub.(0:3) 2.sup.+.sub.(4:6) '+3.sup.+.sub.(0:3) 3 .sub.(4:6) '+4.sub.(0:3) ; and wherein Γ + (α:β) means that at least Γ of said seven bits are "on" over a range α through β of said seven bits, Γ + (α:β)'means that at least Γ of said seven bits are "off" over a range α through β of said seven bits, Γ(α:β) means that exactly Γ of said seven bits are "on" over a range α through β of said seven bits; Γ(α:β)' means that exactly Γ of said seven bits are "off" over a range α-β of said seven bits.

Claim 10

The 7/3 counter of claim 8 wherein said logic means include a plurality of substage means for generating a plurality of logical constructs, said substage means including three first substages, one second substage and one third substage: said first substages receiving said seven bits and generating the constructs 2(0:1), 1 + (0:1), 0(0:1); 2(2:3), 1 + (2:3), 0(2:3); and 3(4:6), 2 + (4:6), 1 + (4:6); said second substage receiving said first stage constructs except 3(4:6), 2 + (4:6) and 1 + (4:6), and generating the constructs 4(0:3), 2 + (0:3), 1 + (0:3); said third substage receiving said second substage constructs and said first substage constructs 3(4:6), 2 + (4:6) and 1 + (4:6), and generating c 1 and c 2 ; and wherein the expression Γ + (α:β) means that at least Γ of said seven bits are "on" over a range α through β of said seven bits and Γ(α:β) means that exactly Γ said seven bits are "on" over a range α-β of said seven bits.