Summing arrangements

Claim 2

A summing arrangement having a plurality of main inputs and operative to produce an output signal indicative of the number of main inputs energized, comprising a plurality of threshold elements each having a plurality of inputs and an output and operative to energize its output when at least a predetermined number, different for each threshold element, of its inputs is energized, means respectively connecting the inputs of each threshold element to a greater number of the main inputs than its respective said predetermined number whereby different combinations of the threshold elements energize their outputs for different numbers of main inputs energized, and logic elements connected to the outputs of the threshold elements in such a manner as to produce said output signal, said logic elements comprising at least one INCLUSIVE or gate, and at least one INHIBIT gate.

Claim 3

An arrangement according to claim 1, in which each threshold element has as many inputs as there are main inputs, and the connecting means connects each of said threshold element inputs to a respective main input, whereby said output signal comprises a binary number representing the number of inputs energized.

Claim 4

An arrangement according to claim 2, in which the logic elements comprise a series of INHIBIT gates each having its output connected to the non-inhibiting one of the inputs of another thereof via a respective two-input OR gate, the first INHIBIT gate in the series having its non-inhibiting input connected to the output of the threshold element having the lowest predetermined number, a further two-input OR gate having one of its inputs connected to the output of the last INHIBIT gate in the said series and its output connected to generate one binary part of the said output signal, means connecting the inhibiting input of the first INHIBIT gate of the said series to the output of the threshold element having the second lowest predetermined number, means respectively connecting the inhibiting inputs of the following INHIBIT gates in the said series to the outputs of alternate ones of the threshold elements in ascending order of predetermined number, means respectively connecting the second inputs of the said OR gates to the outputs of the intervening ones of the threshold elements in ascending order of predetermined number, a further INHIBIT gate having its non-inhibiting input connected to the output of the threshold element having the second lowest predetermined number and its inhibiting input connected to the output of the threshold element having the fourth lowest predetermined number, a further two-input OR gate having one of its inputs connected to the output of the further INHIBIT gate, its other input connected to the output of the threshold element having the sixth lowest predetermined number, and its output connected to generate another binary part of the said output signal, and means connecting the output of the threshold element having the fourth lowest predetermined number to generate a further binary part of the output signal.

Claim 5

A summing arrangement according to claim 1 for adding decimal numbers represented in binary form by energisation of particular ones of the main inputs, in which the inputs of the threshold elements are connected to different combinations of the main inputs.

Claim 6

A summing arrangement according to claim 1 for adding two decimal numbers each of which is represented in binary form by energization of a corresponding number of inputs in a respective group of said main inputs connected from the first input in the group, in which each threshold element has half its inputs respectively connected to main inputs in one of said group and the other half respectively connected to main inputs in the other of said group, each threshold element having an even number of inputs but not all having the same number of inputs.

Claim 7

A summing arrangement according to claim 5, in which the logic elements comprise a plurality of INHIBIT gates each having its noninhibiting input connected to the output of a respective one of the threshold elements whose said predetermined numbers lie in the range 1 through 9 inclusive, a plurality of two-input INCLUSIVE OR gates each having one of its inputs connected to the output of a respective one of the INHIBIT gates and its output connected to feed a respective one of a group of output lines whereon are generated binary signals representing in decimal form said output signal, means connecting the output of the threshold element whose said predetermined number is ten to the inhibit inputs of all the INHIBIT gates, and to a further one of said group of output lines, and means connecting the outputs of the remaining threshold elements to the second inputs of the INCLUSIVE OR gates.

Claim 8

An arrangement according to claim 1, in which each threshold element comprises a fluidic device including a housing having n input apertures, each aperture being closable by a valve, and biasing means acting simultaneously on all the valves to tend to maintain the valves closed, the biasing means acting on the valves with only sufficient force to hold the valves closed if less than m of the n inputs are supplied with fluidic signals.

Claim 9

An arrangement according to claim 7, in which said biasing means comprises a pivotally mounted yoke pivotable into a position in which it closes said valves, and an array of m resilient members urging said yoke into said position.

Claim 10

An arrangement according to claim 7, including an output aperture closed by an output valve, the output valve being maintained closed when fluidic pressure enters the device through the input apertures, and means operable to open the output valve to determine whether the threshold level of the valve has been exceeded.

Claim 11

An arrangement according to claim 7, wherein said biasing means comprises a pivotal member and magnetic means which cooperates magnetically with the pivotal member to close said valves.