US4168530A
Expired / Lapsed
US
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Multiplication circuit using column compression
Assignee: Unisys Corp
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Filing: 1978-02-13
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Granted: 1979-09-18
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Expires: 1998-02-13
Abstract
Abstract A high speed parallel operation, multiplication circuit is provided having a multiplier multiplexor which may function in combination with a column compressor for providing a resultant product, wherein, preferably, the multiplier multiplexor has been implemented using a modified Booth's algorithm, and wherein the column compressor operates to process every column within the same propagation delay whereby every input may create an output in essentially the same propagation time, i.e., true parallel operation requiring preferably no more than an average column propagation delay time.
Inventors
- 👤 Daniel D. Gajski
- 👤 Chandrakant R. Vora
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:17
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5318; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
228 words
A binary multiplication circuit comprising: array generating means for operating upon a binary multiplier and a binary multiplicand for generating a partial product array, through parallel operating circuitry, in a single operation time, said array generating means including a plurality of identical multiplication multiplexors each having correspondingly identical inputs thereof connected to the same bits of said multiplicand input and having other inputs thereof connected to differing bits of said multiplier input, said plurality of multiplication multiplexors including an implementation of Booth's Algorithm; compressing means, being responsive to said array generating means for compressing said array generated, wherein compression of each column of the array is accomplished in parallel within a single operation time, said compressing means including a plurality of identical column compressors connected to the outputs of said plurality of multiplication multiplexors in a parallel operating configuration, said column compressors operating in unison within a single operation time, said plurality of column compressors each performing a parallel compression of a plurality of inputs into two outputs and said plurality of column compressors each including a plurality of gates each gate having at least one inverting input and an inverted and a non-inverted output; and means for providing a final product by an addition operation upon the compressed array from said compressing means, said final product providing means being connected to the output of said compressing means.
Claim 2
Dependent Claim
228 words
A binary multiplication circuit comprising: array generating means for operating upon a binary multiplier and a binary multiplicand for generating a partial product array, through parallel operating circuitry, in a single operation time, said array generating means including a plurality of identical multiplication multiplexors each having correspondingly identical inputs thereof connected to the same bits of said multiplicand input and having other inputs thereof connected to differing bits of said multiplier input, said plurality of multiplication multiplexors including an implementation of Booth's Algorithm; compressing means, being responsive to said array generating means for compressing said array generated, wherein compression of each column of the array is accomplished in parallel within a single operation time, said compressing means including a plurality of identical column compressors connected to the outputs of said plurality of multiplication multiplexors in a parallel operating configuration, said column compressors operating in unison within a single operation time, said plurality of column compressors each performing a parallel compression of a plurality of inputs into two outputs and said plurality of column compressors each including a plurality of gates each gate having at least one inverting input and an inverted and a non-inverted output; and means for providing a final product by an addition operation upon the compressed array from said compressing means, said final product providing means being connected to the output of said compressing means.
Claim 3
Dependent Claim
30 words
The circuit of claim 1 wherein said plurality of multiplication multiplexors each includes a plurality of gates, each gate having an inverting input and an inverted and a non-inverted output.
Claim 4
Dependent Claim
22 words
The circuit of claim 2 wherein said plurality of multiplier multiplexors is four and wherein said plurality of column compressors is eight.
Claim 5
Dependent Claim
41 words
The circuit of claim 3 wherein said addition final product means includes four arithmetic logic units connected in a parallel operating configuration to the outputs of said eight column compressors, said four arithmetic logic units providing a sixteen bit final product.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-09-17 | 1983-03-19 | 1983-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-09-17 | 1987-03-19 | 1987-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-09-17 | 1991-03-19 | 1991-09-18 | $7700.00 | Window Closed / Lapsed |