Method and apparatus for providing a context switch in response to an interrupt in a computer process

Claim 2

In a processor system executing processes, a method for interrupting processes, comprising: associating a specific interrupt start routine (ISR) and interrupt return routine (IRR) with each process, said ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and said IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; executing a first process, said first process associated with a first ISR and first IRR; upon receipt of an interrupt during execution of the first process, executing the first ISR to safely suspend execution of the first process; upon completion of execution of the first ISR, servicing the interrupt by executing a corresponding interrupt process; upon completion of execution of the interrupting process, executing the first IRR to safely return to execution of the first process; and upon completion of execution of the first IRR, continuing execution of the first process.

Claim 3

The method as set forth in claim 1, further comprising the step of storing pointers to starting addresses of the first ISR and first IRR at predetermined locations in the processor system, when execution of the first process is initiated, said step of executing the first ISR comprising retrieving the pointer to the starting address of the ISR from the predetermined location and initiating execution of the ISR at the starting address.

Claim 4

The method as set forth in claim 1, further comprising the step of executing a second process upon completion of execution of the first process, comprising the steps of: upon receipt of an interrupt during execution of the second process, executing a second ISR associated with the second process to safely suspend execution of the second process; upon completion of execution of the second ISR, servicing the interrupt by executing a corresponding interrupt process; upon completion of execution of the interrupting process, executing the second IRR to safely return to execution of the second process; and upon completion of the second IRR, continuing execution of the second process.

Claim 5

The method as set forth in claim 1, wherein said processor system comprises a memory requiring specified voltages to perform operations on the memory, said first ISR comprising steps of removing specified voltages in an orderly manner to insure that the memory is not damaged and data stored in the memory is not corrupted.

Claim 6

The method as set forth in claim 1, wherein said processor system comprises a memory requiring specified voltages to perform operations on the memory, said first IRR comprising steps of applying specified voltages in an orderly manner to enable the first process to continue execution, to insure that the memory is not damaged and data stored in the memory is not corrupted.

Claim 7

The method as set forth in claim 1, wherein said first process comprises steps to erase a Flash memory.

Claim 8

The method as set forth in claim 1, wherein said first process comprises steps to program a Flash memory.

Claim 9

The method as set forth in claim 1, wherein: said step of executing a first ISR comprises the step of switching from a first call stack utilized by the first process, to a second unused call stack, said ISR using the second call stack during execution, wherein upon completion of the first ISR, said second call stack is empty; said step of servicing the interrupt executes a corresponding interrupt process using the second call stack, upon completion of execution of said corresponding interrupt process, said second call stack is empty; and prior to continuing execution of the first process, switching from the second call stack to the first call stack.

Claim 10

The method as set forth in claim 8, wherein: said first process using a first set of register files during execution; upon completion of execution of the first ISR, further switching from said first register files to a second set of register files to enable the state of the first register files to remain intact for later access by the first process and to provide a separate set of register files during execution of the interrupting process; and prior to continuing execution of the first process, switching from the second set of register files to the first set of register files.

Claim 11

The method as set forth in claim 8, further comprising the step of detecting completion of execution of the first ISR by detecting an empty second call stack.

Claim 12

An interrupt mechanism for safely interrupting executing processes executed by a processor on a computer system comprising: at least one interrupt service routine (ISR) and at least one interrupt return routine (IRR), each interruptible process executing having an associated ISR and IRR, each ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and each IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; logic to control sequencing of processes when an interrupt is issued such that an ISR associated with the executing process is executed prior to execution of an interrupt process and an IRR associated with the executing process is executed subsequent to execution of the interrupt process, such that when an interrupt is issued during execution of a first executing process, said processor, prior to servicing the interrupt, executes a first ISR associated with the first process to safely suspend execution of the first process, said processor, upon completion of execution of the first ISR, servicing the interrupt by executing a corresponding interrupt process, said processor, upon completion of execution of the interrupting process, executing a first IRR associated with the first process to safely return to execution of the first process, and upon completion of execution of the first IRR, said processor continuing execution of the first process.

Claim 13

An interrupt mechanism for safely interrupting executing processes executed by a processor on a computer system comprising: at least one interrupt service routine (ISR) and at least one interrupt return routine (IRR), each interruptible process executing having an associated ISR and IRR, each ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and each IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; logic to control sequencing of processes when an interrupt is issued such that an ISR associated with the executing process is executed prior to execution of an interrupt process and an IRR associated with the executing process is executed subsequent to execution of the interrupt process, such that when an interrupt is issued during execution of a first executing process, said processor, prior to servicing the interrupt, executes a first ISR associated with the first process to safely suspend execution of the first process, said processor, upon completion of execution of the first ISR, servicing the interrupt by executing a corresponding interrupt process, said processor, upon completion of execution of the interrupting process, executing a first IRR associated with the first process to safely return to execution of the first process, and upon completion of execution of the first IRR, said processor continuing execution of the first process.

Claim 14

The interrupt mechanism as set forth in claim 11, further comprising a first call stack and second call stack, said first call stack utilized by the first process and said second call stack utilized by the first ISR during execution, and by said second interrupt process during execution.

Claim 15

The interrupt mechanism as set forth in claim 12, further comprising a first set of register files utilized by the first process during execution, and a second set of register files utilized by the interrupting process to enable the state of the first register files to remain intact for later access by the first process and to provide a separate set of register files during execution of the interrupting process.

Claim 16

A computer system comprising: a processor that executes processes; a memory coupled to the processor; an interrupt mechanism comprising at least one interrupt start routine (ISR) and at least one interrupt return routine (IRR), each interruptible process executing having an associated ISR and IRR, each ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and each IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; logic to control sequencing of processes when an interrupt is issued such that an associated ISR is executed prior to execution of an interrupt process and an associated IRR is executed subsequent to execution of the interrupt process, such that when an interrupt is issued during execution of a first executing process, said processor, prior to servicing the interrupt, executes a first ISR associated with the first process to safely suspend execution of the first process, said processor, upon completion of execution of the first ISR, servicing the interrupt by execution a corresponding interrupt process, said processor, upon completion of execution of the interrupting process, executing a first IRR associated with the first process to safely return to execution of the first process, and upon completion of execution of the first IRR, said processor continuing execution of the first process.

Claim 17

A computer system comprising: a processor that executes processes; a memory coupled to the processor; an interrupt mechanism comprising at least one interrupt start routine (ISR) and at least one interrupt return routine (IRR), each interruptible process executing having an associated ISR and IRR, each ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and each IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; logic to control sequencing of processes when an interrupt is issued such that an associated ISR is executed prior to execution of an interrupt process and an associated IRR is executed subsequent to execution of the interrupt process, such that when an interrupt is issued during execution of a first executing process, said processor, prior to servicing the interrupt, executes a first ISR associated with the first process to safely suspend execution of the first process, said processor, upon completion of execution of the first ISR, servicing the interrupt by execution a corresponding interrupt process, said processor, upon completion of execution of the interrupting process, executing a first IRR associated with the first process to safely return to execution of the first process, and upon completion of execution of the first IRR, said processor continuing execution of the first process.

Claim 18

The computer system as set forth in claim 14, wherein the memory is a flash EEPROM memory requiring specified voltages to perform operations on the memory, said first ISR comprising steps of removing specified voltages in an orderly manner to insure that the memory is not damaged and data stored in the memory is not corrupted.

Claim 19

The computer system as set forth in claim 14, wherein the memory is a flash EEPROM memory requiring specified voltages to perform operations on the memory, said first IRR comprising steps of applying specified voltages in an orderly manner to enable the first process to continue execution, to insure that the memory is not damaged and data stored in the memory is not corrupted.

Claim 20

The computer system as set forth in claim 14, further comprising a first call stack and second call stack, said first call stack utilized by the first process and said second call stack utilized by the first ISR during execution, and by said second interrupt process during execution.

Claim 21

The computer system as set forth in claim 17, further comprising a first set of register files utilized by the first process during execution, and a second set of register files utilized by the interrupting process to enable the state of the first register files to remain intact for later access by the first process and to provide a separate set of register files during execution of the interrupting process.

Claim 22

An interrupt mechanism for safely interrupting executing processes executed by a processor on a computer system comprising: at least one interrupt service routine (ISR) and at least one interrupt return routine (IRR), each interruptible process executing having an associated ISR and IRR, each ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and each IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; means for controlling sequencing of processes when an interrupt is issued such that an associated ISR is executed prior to execution of an interrupt process and an associated IRR is executed subsequent to execution of the interrupt process, such that when an interrupt is issued during execution of a first executing process, said processor, prior to servicing the interrupt, executes a first ISR associated with the first process to safely suspend execution of the first process, said processor, upon completion of execution of the first ISR, servicing the interrupt by execution a corresponding interrupt process, said processor, upon completion of execution of the interrupting process, executing a first IRR associated with the first process to safely return to execution of the first process, and upon completion of execution of the first IRR, said processor continuing execution of the first process.

Claim 23

An interrupt mechanism for safely interrupting executing processes executed by a processor on a computer system comprising: at least one interrupt service routine (ISR) and at least one interrupt return routine (IRR), each interruptible process executing having an associated ISR and IRR, each ISR comprising steps, when executed, to safely suspend execution of the corresponding process without corruption of the system or data and enable an interrupting process to execute, and each IRR comprising steps, when executed, to safely resume execution of the corresponding process without corruption of the system or data; means for controlling sequencing of processes when an interrupt is issued such that an associated ISR is executed prior to execution of an interrupt process and an associated IRR is executed subsequent to execution of the interrupt process, such that when an interrupt is issued during execution of a first executing process, said processor, prior to servicing the interrupt, executes a first ISR associated with the first process to safely suspend execution of the first process, said processor, upon completion of execution of the first ISR, servicing the interrupt by execution a corresponding interrupt process, said processor, upon completion of execution of the interrupting process, executing a first IRR associated with the first process to safely return to execution of the first process, and upon completion of execution of the first IRR, said processor continuing execution of the first process.