Clock generating circuit, PLL circuit, semiconductor device, and methods for designing and making the clock generating circuit

Claim 2

A circuit for generating a clock having a multiplied frequency, comprising: a plurality of delay lines connected in cascade to which a first clock is to be inputted; logic circuits to which the first clock and a second clock outputted from each of the delay lines are to be inputted, the logic circuits being alternately connected in cascade to the delay lines; a frequency comparing circuit to which the outputs from each of said logic circuits are to be inputted; a phase comparator to which the first clock and the second clock outputted from the delay line in the last stage are to be inputted; and a control circuit for controlling the delay time of the delay lines on the basis of an output signal of the phase comparator, wherein the control circuit controls the delay time of the delay lines on the basis of an output signal of the phase comparator when the output signal of the frequency comparing circuit is at a predetermined logic level.

Claim 3

A circuit for generating a clock having a multiplied frequency, comprising: a plurality of delay lines connected in cascade to which a first clock is to be inputted; and a logic circuit unit to which the first clock and a second clock outputted from each of the delay lines are to be inputted, wherein each of the delay lines includes a first delay line section and a second delay line section, and each of the delay lines generates maximum delay time (M×T1)+(N×T2) in the time resolution T2 on condition that (N+1)×T2≧T1 and T2<T1 where each of the first and the second delay line sections is controlled by an independent delay time selecting signal; each of the first and the second delay line sections includes a plurality of delay units; each and every delay unit of the first delay line section has an inherent delay time T1; each and every delay unit of the second delay line section has an inherent delay time T2; and the first delay line section includes M-number of the delay units and the second delay line section includes N-number of the delay units.

Claim 4

A circuit for generating a clock having a multiplied frequency, comprising: a plurality of delay lines connected in cascade to which a first clock is to be inputted; and a logic circuit unit to which the first clock and a second clock outputted from each of the delay lines are to be inputted, wherein each of the delay lines includes a first delay line section and a second delay line section, and each of the delay lines generates maximum delay time (M×T1)+(N×T2) in the time resolution T2 on condition that (N+1)×T2≧T1 and T2<T1 where each of the first and the second delay line sections is controlled by an independent delay time selecting signal; each of the first and the second delay line sections includes a plurality of delay units; each and every delay unit of the first delay line section has an inherent delay time T1; each and every delay unit of the second delay line section has an inherent delay time T2; and the first delay line section includes M-number of the delay units and the second delay line section includes N-number of the delay units.

Claim 5

A circuit for generating a clock having a multiplied frequency, comprising: a plurality of delay lines connected in cascade to which a first clock is to be inputted; a logic circuit unit to which the first clock and a second clock outputted from each of the delay lines are to be inputted; a first phase comparator and a second phase comparator to which the first clock and the second clock outputted from the delay line in the last stage are to be inputted; a first control circuit for controlling the delay time of a first delay line section on the basis of an output signal of the first phase comparator; a second control circuit for controlling the delay time of a second delay line section on the basis of an output signal of the second phase comparator; and a lock detecting circuit for detecting a lock condition of a clock on the basis of the output signal of the first phase comparator, and controlling the let-in and shut-out of the output signals of the second phase comparator and the second control circuit, wherein each of the delay lines includes the first delay line section and the second delay line section, each of the first and second delay line sections includes a plurality of delay units connected in cascade, and the delay times of the delay units in the first and second delay line sections are differentiated from each other.

Claim 6

A circuit for generating a clock having a multiplied frequency, comprising: a plurality of delay lines connected in cascade to which a first clock is to be inputted; a logic circuit unit to which the first clock and a second clock outputted from each of the delay lines are to be inputted; a first phase comparator and a second phase comparator to which the first clock and the second clock outputted from the delay line in the last stage are to be inputted; a first control circuit for controlling the delay time of a first delay line section on the basis of an output signal of the first phase comparator; a second control circuit for controlling the delay time of a second delay line section on the basis of an output signal of the second phase comparator; and a lock detecting circuit for detecting a lock condition of a clock on the basis of the output signal of the first phase comparator, and controlling the let-in and shut-out of the output signals of the second phase comparator and the second control circuit, wherein each of the delay lines includes the first delay line section and the second delay line section, each of the first and second delay line sections includes a plurality of delay units connected in cascade, and the delay times of the delay units in the first and second delay line sections are differentiated from each other.

Claim 7

A PLL circuit for synchronizing the phases of clocks, comprising: a clock generating circuit of claim 3; a phase synchronizing circuit to which an output clock of the clock generating circuit is to be inputted; and a waveform shaping circuit to which an output of the phase synchronizing circuit is to be inputted, wherein the first clock is to be inputted to the clock generating circuit and phase synchronizing circuit, and an output clock of the waveform shaping circuit is to be inputted to the phase synchronizing circuit.

Claim 8

A PPL circuit for synchronizing the phases of clocks, comprising: a phase synchronizing circuit; and a clock generating circuit of claim 3 to which an output clock of the phase synchronizing circuit is to be inputted as said first clock.

Claim 9

A semiconductor device including the clock generating circuit of claim 3.

Claim 12

A process for manufacturing a clock generating circuit, comprising steps of: connecting the number K of delay units in cascade so as to construct a delay line; K≧ {1/(2·N·F.sub.ref)}-(T.sub.mul)!/(T.sub.dmin) where F ref : a lower limit of the frequency of a clock whose frequency is to be multiplied N: a frequency multiplication number T dmin : a minimum value of a delay time proper to the delay unit T mul : a minimum delay time of the delay line connecting the plurality of delay lines in cascade; and connecting an output terminal of each of the delay lines to a logic circuit.

Claim 13

A process for manufacturing a clock generating circuit, comprising steps of: connecting the number K of delay units in cascade so as to construct a delay line; K≧ {1/(2·N·F.sub.ref)}-(T.sub.mul)!/(T.sub.dmin) where F ref : a lower limit of the frequency of a clock whose frequency is to be multiplied N: a frequency multiplication number T dmin : a minimum value of a delay time proper to the delay unit T mul : a minimum delay time of the delay line connecting the plurality of delay lines in cascade; and connecting an output terminal of each of the delay lines to a logic circuit.

Claim 14

A circuit for generating a clock having a multiplied frequency, said circuit comprising: a first delay line arranged to receive a first clock signal and generating a delayed first clock signal; a first logic circuit arranged to receive said first clock signal and said delayed first clock signal and generating a second clock signal; a second delay line arranged to receive said second clock signal and generating a delayed second clock signal; and a second logic circuit arranged to receive said first clock signal and said delayed second clock signal and generating a third clock signal, wherein each of the first and second delay lines includes a plurality of delay units connected in cascade, each of which has two switching elements for letting in or shutting out a clock, and a delay element connected to both of the switching elements.

Claim 15

A circuit for generating a clock having a multiplied frequency, said circuit comprising: a first delay line arranged to receive a first clock signal and generating a delayed first clock signal; a first logic circuit arranged to receive said first clock signal and said delayed first clock signal and generating a second clock signal; a second delay line arranged to receive said second clock signal and generating a delayed second clock signal; and a second logic circuit arranged to receive said first clock signal and said delayed second clock signal and generating a third clock signal, wherein each of the first and second delay lines includes a plurality of delay units connected in cascade, each of which has two switching elements for letting in or shutting out a clock, and a delay element connected to both of the switching elements.

Claim 16

The clock generating circuit according to claim 9, wherein each of the delay lines includes a selecting means for selecting one of the delay units so as to input the first clock to one of the switching elements of the selected delay unit.