High-speed complementary multiplexer

Claim 2

A multiplexer, comprising: a PMOS pass-gate having a first threshold voltage connected to a first input line, an output, and a select line, for passing a first input signal received along said first input line, said first input signal received along said first input line being passed by said PMOS pass-gate only if a select signal received along said select line is in a first state; an NMOS pass-gate having a second threshold voltage, connected to a second input line, an output and said select line, for passing a second input signal received along said second input line, said second input signal received along said second input line being passed by said NMOS pass-gate only if said select signal received along said select line is in a second state; and a compensation unit, connected to outputs of said PMOS and NMOS pass-gates, for receiving a signal passed through one of said pass-gates and for compensating for said threshold voltage differences between said PMOS and NMOS pass-gates such that a range of output voltages provided by said multiplexer is substantially unaffected by whether said signal is passed through said PMOS pass-gate or through said NMOS pass-gate.

Claim 3

The multiplexer of claim 1, wherein said PMOS pass-gate comprises a first PMOS transistor, having a gate connected to said select line, for passing said first input signal in response to a low voltage signal received along said select line; and wherein said NMOS pass-gate comprises a first NMOS transistor, having a gate connected to said select line, for passing said second input signal in response to a high voltage signal received along said select line.

Claim 4

The multiplexer of claim 2, wherein said compensation unit comprises: a second PMOS transistor having a gate connected to said output of said first PMOS transistor, a source connected to a high voltage level, and a drain connected to an output line; a second NMOS transistor having a gate connected to said output of said first NMOS transistor, a source connected to a ground, and a drain connected to said output line; a third NMOS transistor having a gate connected to said select input line, a drain connected to said output line, and a source; a fourth NMOS transistor having a gate connected to said second input line, a source connected to a ground, and a drain connected to said source of said third NMOS transistor; and a line interconnecting said output of said first PMOS transistor and said output of said first NMOS transistor.

Claim 5

The multiplexer of claim 2, wherein said compensation unit comprises: a second PMOS transistor having a gate connected to said first input line, a source connected to a high voltage source, and a drain; a third PMOS transistor having a gate connected to said select input line, a source connected to said drain of said second PMOS transistor, and a drain; a fourth PMOS transistor having a gate connected to an output of said first PMOS transistor, a source connected to said high voltage source, and a drain; a bipolar transistor, having a collector connected to said high voltage source, a base connected to said drains of said third and fourth PMOS transistors, and an emitter connected to an output line; a second NMOS transistor having a gate connected to an output of said first NMOS transistor, a source connected to a ground, and a drain connected to said drains of said third and fourth PMOS transistors; and a third NMOS transistor having a source connected to a ground, a gate connected to said output of said first NMOS transistor, and a drain connected to an output line.

Claim 8

The method of claim 5, wherein said PMOS pass-gate is a first PMOS transistor having a gate connected to said select input line and wherein said step of passing said first input signal through a PMOS pass-gate comprises the steps of: applying said select signal to said gate of said first PMOS transistor; and applying said first input signal to an input of said first PMOS transistor; and wherein said NMOS pass-gate is a first NMOS transistor having a gate connected to said select input line and wherein said step of passing said second input signal through a second pass-gate comprises the steps of: applying said select signal to said gate of said first NMOS transistor; and applying said second input signal to an input of said first NMOS transistor.

Claim 9

The method of claim 6, wherein said step of compensating for voltage differences comprises the steps of: applying an output of said first PMOS transistor to the gates of a second PMOS transistor, wherein said second PMOS transistor has a source, connected to a high voltage source, and a drain connected to an output line; applying the output of said first PMOS transistor to the gates of a second NMOS transistor, wherein said second NMOS transistor has a drain connected to the output line, and a source connected to a ground; applying said select signal to a third NMOS transistor, wherein said third NMOS transistor has a drain connected to said output line and a source; and applying said second input signal to a fourth NMOS transistor, wherein said fourth NMOS transistor has a drain connected to the source of said third NMOS transistor and a drain connected to a ground.

Claim 10

The method of claim 6, wherein said step of scaling said signal comprises the steps of: applying said first input signal to a gate of a second PMOS transistor, said second PMOS transistor having a source connected to a high voltage source, and a drain; applying said select signal to a gate of a third PMOS transistor, said third PMOS transistor having a source, connected to said drain of said second PMOS transistor, and a drain; applying an output of said first PMOS transistor to a gate of a fourth PMOS transistor, said fourth PMOS transistor having a source, connected to said high voltage source, and a drain; applying an output of said first NMOS transistor to a gate of a second NMOS transistor, said second NMOS transistor having a source connected to a ground, and a drain connected to said drains of said third and fourth PMOS transistors; applying said drains of said third and fourth PMOS transistors and said second NMOS transistor to a base of a bipolar transistor, said bipolar transistor having a collector connected to said high voltage source, and an emitter connected to an output line; and applying said output of said first NMOS transistor to a gate of a third NMOS transistor, said third NMOS transistor having a source connected to a ground and a drain connected to the output line.