BiCMOS circuit

Claim 2

A BiCMOS logic gate providing both inverting and non-inverting output signals comprising: a bipolar transistor having its collector coupled to a first operating potential, its base connected to an input node and its emitter coupled to a non-inverting output node; a first field-effect device coupled between said non-inverting output node and a second operating potential; second and third field-effect coupled as a CMOS inverter connected between said first and second operating potentials, the inverting output node of said inverter being coupled to the gate of said first field-effect device and also providing said inverting output signal of said circuit; a fourth field-effect connected between said first operating potential and said non-inverting output node, the gate of said fourth field-effect device being driven by said inverting output node; the gates of said second and third field-effect devices being connected to said input node such that when a logical high signal is applied to said input node said non-inverting output node is driven to a high logic state approximately equal to said first operating potential and said inverting output node is driven to a low logic state approximately equal to said second operating potential, and when a logic low signal is applied to said input node said non-inverting output node is driven to said low logic state and said inverting output node is driven to said high logic state.

Claim 3

The circuit of claim 1 wherein said first operating potential is a high positive supply potential, and said second operating potential is ground.

Claim 4

The circuit of claim 2 wherein said bipolar transistor comprises an NPN transistor.

Claim 5

The circuit of claim 3 wherein said first and third field-effect devices comprise n-channel MOS transistors, and said second and fourth field-effect devices comprise p-channel MOS transistors.

Claim 6

The circuit of claim 4 wherein switching occurs in said circuit from a high-to-low state whenever said input node falls one p-channel MOS voltage threshold below said high positive supply potential.

Claim 7

The circuit of claim 2 further comprising latching means for latching either said high or low logic state in the absence of a logical signal being applied to said input node, the propagation delay of data through said circuit being unaffected by said latching means.

Claim 8

The circuit of claim 6 wherein said latching means comprises fifth and sixth field-effect devices coupled in a CMOS inverter configuration between said first and second operating potentials, the gates of said fifth and sixth devices being coupled to said inverting output node and their drains being coupled to the base of said bipolar transistor.

Claim 9

A BiCMOS circuit providing both inverting and non-inverting output nodes, each capable of driving relatively large capacitive loads, comprising: a first bipolar transistor having its collector coupled to a first operating potential, its base connected to an input node and its emitter coupled to said non-inverting output node; a second bipolar transistor having its collector coupled to said first operating potential and its emitter coupled to said inverting output node; a first field-effect device coupled between said non-inverting output node and a second operating potential, the gate of said first field-effect device being coupled to said inverting output node; a second and third field-effect devices coupled in a CMOS inverter configuration between said first and second operating potentials, the drains of said second and third devices driving the base of said second bipolar transistor; a fourth field-effect device connected between said inverting output node and said second operating potential, the gate of said fourth field-effect device being coupled to said input node; fifth and sixth field-effect devices coupled between said first operating potential and said non-inverting and inverting output nodes, respectively, the gate of said fifth field-effect device being coupled to said inverting output node, while the gate of said sixth field-effect device being coupled to said non-inverting output node; the gates of said second and third field-effect devices being connected to said input node such that when a logical high signal is applied to said input node said non-inverting output node is charged to a high logic state approximately equal to said first operating potential while said inverting output node is discharged to a low logic state approximately equal to said second operating potential, and when a logical low signal is applied to said input node said non-inverting output node is discharged to said low logic state while said inverting output node is charged to said high logic state.

Claim 10

A BiCMOS circuit providing both inverting and non-inverting output nodes, each capable of driving relatively large capacitive loads, comprising: a first bipolar transistor having its collector coupled to a first operating potential, its base connected to an input node and its emitter coupled to said non-inverting output node; a second bipolar transistor having its collector coupled to said first operating potential and its emitter coupled to said inverting output node; a first field-effect device coupled between said non-inverting output node and a second operating potential, the gate of said first field-effect device being coupled to said inverting output node; a second and third field-effect devices coupled in a CMOS inverter configuration between said first and second operating potentials, the drains of said second and third devices driving the base of said second bipolar transistor; a fourth field-effect device connected between said inverting output node and said second operating potential, the gate of said fourth field-effect device being coupled to said input node; fifth and sixth field-effect devices coupled between said first operating potential and said non-inverting and inverting output nodes, respectively, the gate of said fifth field-effect device being coupled to said inverting output node, while the gate of said sixth field-effect device being coupled to said non-inverting output node; the gates of said second and third field-effect devices being connected to said input node such that when a logical high signal is applied to said input node said non-inverting output node is charged to a high logic state approximately equal to said first operating potential while said inverting output node is discharged to a low logic state approximately equal to said second operating potential, and when a logical low signal is applied to said input node said non-inverting output node is discharged to said low logic state while said inverting output node is charged to said high logic state.

Claim 11

The circuit of claim 8 wherein said first operating potential is a high positive supply potential, and said second operating potential is ground.

Claim 12

The circuit of claim 9 wherein said first and second bipolar transistors comprise NPN transistors.

Claim 13

The circuit of claim 10 wherein said first, third, and fourth field-effect devices comprise n-channel MOS transistors, and said second, fifth, and sixth field-effect devices comprise p-channel MOS transistors.

Claim 14

The circuit of claim 11 wherein switching occurs within said circuit from a high-to-low state whenever said input node falls one p-channel MOS voltage threshold below said high positive supply potential.