US5491673A
Expired / Lapsed
US
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Timing signal generation circuit
Assignee: Advantest Corp
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Filing: 1994-11-30
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Granted: 1996-02-13
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Expires: 2014-11-30
Abstract
Abstract A timing generator which is capable of generating a timing signal with high resolution and accuracy which is not affected by the changes in temperature and power supply voltage or the self-generated heat of the circuit component. The timing signal generator can generate a timing signal which has a delay time combined with a large delay time which is greater than the clock signal period and a small delay time which is smaller than the clock signal period. The timing signal generator includes a plurality of variable delay devices serially connected one another, a phase comparator which compares a total delay time of the variable delay devices with a clock signal and generates a voltage signal indicative of the difference between the two, a feed back circuit that feeds back the voltage signal from the phase comparator to the variable delay devices to form a phase locked loop so that the total delay time in the variable delay devices is equal to the one period of the clock signal, a synchronous delay circuit for generating a large delay time which is proportional to the clock signal period, a selector circuit for selecting one combination of the large delay time from the synchronous delay circuit and a small delay time from one of the variable delay devices.
Inventors
- 👤 Toshiyuki Okayasu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:36
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
196 words
A timing signal generation circuit, comprising: a plurality of variable delay devices serially connected one another, each variable delay device having a propagation time delay which is substantially smaller than one period of a clock signal; a phase comparator which compares a total delay time of said variable delay devices derived from the last stage of said variable delay devices with said clock signal and generates a voltage signal indicative of the difference between the two; a feed back circuit that feeds back said voltage signal from said phase comparator to said variable delay devices to form a phase locked loop so that said total delay time of said variable delay devices is equal to the one period of said clock signal; a synchronous delay circuit provided with said clock signal for generating a large delay time which is proportional to said clock signal period; a selector circuit which is provided with said large delay time from said synchronous delay circuit and small delay times from said variable delay devices for selecting one combination of said large delay time from said synchronous delay circuit and a small delay time from one of said variable delay devices.
Claim 2
Dependent Claim
196 words
A timing signal generation circuit, comprising: a plurality of variable delay devices serially connected one another, each variable delay device having a propagation time delay which is substantially smaller than one period of a clock signal; a phase comparator which compares a total delay time of said variable delay devices derived from the last stage of said variable delay devices with said clock signal and generates a voltage signal indicative of the difference between the two; a feed back circuit that feeds back said voltage signal from said phase comparator to said variable delay devices to form a phase locked loop so that said total delay time of said variable delay devices is equal to the one period of said clock signal; a synchronous delay circuit provided with said clock signal for generating a large delay time which is proportional to said clock signal period; a selector circuit which is provided with said large delay time from said synchronous delay circuit and small delay times from said variable delay devices for selecting one combination of said large delay time from said synchronous delay circuit and a small delay time from one of said variable delay devices.
Claim 3
Dependent Claim
48 words
A timing signal generation circuit as defined in claim 1, further including: a plurality of said synchronous delay circuits and a plurality of said selector circuits for generating a plurality of timing signals including the small delay times formed by said variable delay devices at the same time.
Claim 4
Dependent Claim
64 words
A timing signal generation circuit as defined in claim 1, wherein said synchronous delay circuit forms said large delay time which is an integer multiple of said clock signal period and said variable delay devices form said small delay time which is an integer multiple of 1/m clock signal period, wherein m is the number of said variable delay devices serially connected one another.
Claim 5
Dependent Claim
66 words
A timing signal generation circuit as defined in claim 1, wherein said selector circuit is controlled by delay data provided to said synchronous delay circuit and to a decoder, said synchronous delay circuit utilizes upper digits of said delay data to form said large delay time, said decoder utilizes lower digits of said delay data for forming a selector signal to select said small delay time.
Claim 6
Dependent Claim
39 words
A timing signal generation circuit as defined in claim 1, wherein a delay element is further provided between said synchronous delay circuit and said selector circuit to adjust the timing between large delay time and said small delay time.
Claim 7
Dependent Claim
47 words
A timing signal generation circuit as defined in claim 1, wherein said variable delay devices are formed with close proximity in a semiconductor chip to have the same propagation delay time to one another, said propagation delay time being controllable by a change in a supply voltage.
Claim 8
Dependent Claim
37 words
A timing signal generation circuit as defined in claim 2, wherein said plurality of selector circuits are provided with said voltage signal from said feedback circuit to control the signal propagation delay time in said selector circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-12 | 1999-08-14 | 2000-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-12 | 2003-08-14 | 2004-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-12 | 2007-08-14 | 2008-02-13 | $7700.00 | Window Closed / Lapsed |