US5798562A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having an isolation layer and two passivation layers with edges that are not aligned with each other
Assignee: US Philips Corp
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Filing: 1996-10-28
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Granted: 1998-08-25
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Expires: 2016-10-28
Abstract
Abstract The invention relates to a semiconductor device with a substrate, with at least one isolation layer with at least one window, with a passivation layer scheme lying on the isolation layer and a metallization lying on the passivation layer scheme, the latter comprising at least two dielectric layers of which the first dielectric layer covers the isolation layer with its edges as well as the substrate in an outer edge zone of the window, and of which the second dielectric layer covers the first dielectric layer also over the edge of the isolation layer and in a portion of the outer region of the window.
Inventors
- 👤 Johannes Rabovsky
- 👤 Bernd Sievers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:39
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/147
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
134 words
A semiconducting device with a substrate, an isolation layer having a window defining an edge of the isolation layer, a passivation layer scheme lying on the isolation layer, and a metallization lying on the passivation layer scheme, wherein the passivation layer scheme comprises first and second dielectric layers, the first dielectric layer covering the isolation layer and the edge of the isolation layer and extending beyond the edge of the isolation layer to cover a portion of the substrate in the window adjacent the edge of the isolation layer, and the second dielectric layer covering the first dielectric layer everywhere that the first dielectric layer overlies the isolation layer and the edge of the isolation layer but which extends beyond the edge of the isolation layer not as far as the first dielectric layer.
Claim 2
Dependent Claim
134 words
A semiconducting device with a substrate, an isolation layer having a window defining an edge of the isolation layer, a passivation layer scheme lying on the isolation layer, and a metallization lying on the passivation layer scheme, wherein the passivation layer scheme comprises first and second dielectric layers, the first dielectric layer covering the isolation layer and the edge of the isolation layer and extending beyond the edge of the isolation layer to cover a portion of the substrate in the window adjacent the edge of the isolation layer, and the second dielectric layer covering the first dielectric layer everywhere that the first dielectric layer overlies the isolation layer and the edge of the isolation layer but which extends beyond the edge of the isolation layer not as far as the first dielectric layer.
Claim 3
Dependent Claim
23 words
A semiconductor device as claimed in claim 1, characterized in that the first and second dielectric layers each have a uniform layer thickness.
Claim 4
Dependent Claim
41 words
A semiconductor device as claimed in claim 2, characterized in that it has two isolation layers, the first isolation layer consisting of a thermally generated silicon oxide and the second isolation layer consisting of a thermally generated silicon oxide comprising phosphorus.
Claim 5
Dependent Claim
30 words
A semiconductor device as claimed in claim 3, characterized in that the first dielectric layer is made of silicon nitride and the second dielectric layer is made of silicon dioxide.
Claim 6
Dependent Claim
32 words
A semiconductor device as claimed in claim 3, characterized in that the first dielectric layer is made of silicon oxide or silicon nitride and the second dielectric layer is made of polyimide.
Claim 7
Dependent Claim
29 words
A semiconductor device as claimed in claim 3, characterized in that the first dielectric layer is made of polyimide and the second dielectric layer is made of silicon nitride.
References Cited (Backward Citations)
US4001870A
Cited
US3985597A
Cited
US4091406A
Cited
US4328262A
Cited
US4733289A
Cited
US4440580A
Cited
US4477965A
Cited
US4618878A
Cited
US4600624A
Cited
US4601939A
Cited
US4778774A
Cited
US4786610A
Cited
US5055906A
Cited
JPH0237747A
Cited
US5016069A
Cited
US5013674A
Cited
US5616960A
Cited
US5384271A
Cited
US5523616A
Cited
US5366911A
Cited
US5619064A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-24 | 2002-02-23 | 2002-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-24 | 2006-02-23 | 2006-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-24 | 2010-02-23 | 2010-08-25 | $7700.00 | Window Closed / Lapsed |