VLSI process with global planarization

Claim 1

The method of fabricating an integrated circuit wherein global planarization is maintained throughout the process flow comprising: providing trenched isolation regions within a silicon substrate; forming trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions; forming source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions, said trenched polysilicon gate electrodes, and said source and drain regions form a planarized top surface of said silicon substrate; depositing a pre-metal dielectric layer over said planarized top surface of said silicon substrate; etching through said pre-metal dielectric to form contact openings to said trenched polysilicon gate electrodes and to said source and drain regions; filling said contact openings with metal plugs wherein the top surfaces of said pre-metal dielectric and said metal plugs form a planarized top surface of said silicon substrate; depositing a first metal layer over said planarized top surface of said silicon substrate; implanting oxygen ions into portions of said first metal layer not covered by a mask wherein said portions of said first metal layer are transformed into an insulator layer and wherein the top surface of said first metal layer forms a planarized top surface of said silicon substrate; depositing an inter-metal dielectric layer over said top planarized surface of said silicon substrate; etching through said inter-metal dielectric to form contact openings to said first metal layer; filling said contact openings with metal plugs wherein the top surfaces of said inter-metal dielectric and said metal plugs form a planarized top surface of said silicon substrate; depositing a second metal layer over said planarized top surface of said silicon substrate; implanting oxygen ions into said portions of said second metal layer not covered by a mask wherein said second metal layer is transformed into an insulator layer and wherein the top surface of said second metal layer forms a planarized top surface of said silicon substrate; and covering said planarized top surface of said silicon substrate with a passivation layer to complete fabrication of said integrated circuit wherein global planarization is maintained throughout the process flow.

Claim 2

The method of fabricating an integrated circuit wherein global planarization is maintained throughout the process flow comprising: providing trenched isolation regions within a silicon substrate; forming trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions; forming source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions, said trenched polysilicon gate electrodes, and said source and drain regions form a planarized top surface of said silicon substrate; depositing a pre-metal dielectric layer over said planarized top surface of said silicon substrate; etching through said pre-metal dielectric to form contact openings to said trenched polysilicon gate electrodes and to said source and drain regions; filling said contact openings with metal plugs wherein the top surfaces of said pre-metal dielectric and said metal plugs form a planarized top surface of said silicon substrate; depositing a first metal layer over said planarized top surface of said silicon substrate; implanting oxygen ions into portions of said first metal layer not covered by a mask wherein said portions of said first metal layer are transformed into an insulator layer and wherein the top surface of said first metal layer forms a planarized top surface of said silicon substrate; depositing an inter-metal dielectric layer over said top planarized surface of said silicon substrate; etching through said inter-metal dielectric to form contact openings to said first metal layer; filling said contact openings with metal plugs wherein the top surfaces of said inter-metal dielectric and said metal plugs form a planarized top surface of said silicon substrate; depositing a second metal layer over said planarized top surface of said silicon substrate; implanting oxygen ions into said portions of said second metal layer not covered by a mask wherein said second metal layer is transformed into an insulator layer and wherein the top surface of said second metal layer forms a planarized top surface of said silicon substrate; and covering said planarized top surface of said silicon substrate with a passivation layer to complete fabrication of said integrated circuit wherein global planarization is maintained throughout the process flow.