Large-scale EPROM memory

Claim 2

A memory having multiple memory points comprising: multiple floating gate MOS transistors arranged on a substrate to correlate with the respective memory points, each of the transistors including a control gate, a floating gate, a source, and a drain region of a first conductivity type, plural word lines extending in a first direction, each of the word lines interconnecting the transistor control gates of a first group of transistors, plural bit lines extending in a second direction, the first and second directions differing from each other by 90°, each of the bit lines interconnecting the transistor drains of a second group of transistors, the drain region of each transistor in the second group extending in the second direction to form one of the bit lines, said word lines addressing a selected transistor row and said bit lines transmitting a signal indicative of a logic state of the transistors; plural constant-potential lines extending in the second direction, each of the constant potential lines interconnecting the sources of one group of transistors, each of the constant-potential lines including a diffusion of the first conductivity type and being positioned between a pair of adjacent bit lines, all of the contact-potential lines being at the same potential, a plurality of dielectric isolation areas extending in the second direction, each of the isolation areas being positioned on the side of each bit line opposite to one of the constant-potential lines, and plural conductive areas extending in the second direction, each of said conductive areas covering one of said isolation areas.

Claim 3

The memory of claim 1 wherein each of said conductive areas floats with respect to said word lines, bit lines and substrate.

Claim 4

The memory of claim 1 wherein the conductive areas and floating gates are formed of the same material.

Claim 5

The memory of claim 3 wherein said conductive areas (E) are formed during the same manufacturing step as the floating gates of said transistors.

Claim 6

The memory of claim 1 wherein the floating gate of each transistor of said one group is mainly formed by a conductive rectangle located over a second conductivity type area forming a channel of said transistor; the transistors of said one group being in two adjacent rows and two columns on each side of one constant-potential line; the channels of two adjacent transistors of one column being spaced by a region having the second conductivity type; the channels of two transistors being in one row, the two transistors being arranged on both sides of a given constant-potential line, the channels of the two transistors being adjacent a single region of the first conductivity type, the single region separating said two transistors and forming the source of the two transistors; and ends of the channels of said two transistors opposite to the region corresponding to the source being adjacent a region of the first conductivity type corresponding to the drain of each of said two transistors.

Claim 7

The memory of claim 1 wherein the conductive area covering said isolation area, and the floating gates are formed of polycrystalline silicon.

Claim 8

The memory of claim 1 wherein said conductive area covering said isolation area projects a predetermined distance from each side of the isolation region in a direction parallel to the word lines.

Claim 9

The memory of claim 2 wherein each of said conductive areas covering said isolation areas and the floating gates are arranged to have a constant pitch in the first direction.

Claim 10

The memory of claim 2 wherein each transistor includes: a silicon dioxide layer having a thickness less than 20 nm separating the channel from the floating gate, and wherein the sources are formed of a highly doped section arranged in a pocket having the first conductivity type and a low doping level, whereby electrons may tunnel through the silicon dioxide layer from the floating gates to the highly doped source region in response to a selected voltage being applied to the source, whereby the memory is electrically erasable.

Claim 11

A memory having multiple memory points comprising: multiple floating gate MOS transistors arranged on a substrate to correlate with the respective memory points, each of the transistors including a control gate, a floating gate, a source, a drain region of a first conductivity type, a gate oxide layer between the floating gate and the substrate, and a channel in the substrate between the source and drain controlled by voltage applied to the control gate through the gate oxide layer and the floating gate, plural work lines extending in a first direction, each of the word lines interconnecting the transistor control gates of a first group of transistors, plural bit lines extending in a second direction, the first and second directions differing from each other by 90°, each of the bit lines interconnecting the transistor drains of a second group of transistors, the drain region of each transistor in the second group extending in the second direction to form one of the bit lines, said word lines addressing a selected transistor row and said bit lines transmitting a signal indicative of a logic state of the transistors; plural constant-potential lines extending in the second direction, each of the constant potential lines interconnecting the sources of one group of transistors, each of the constant-potential lines including a diffusion of the first conductivity type and being positioned between a pair of adjacent bit lines, all of the constant-potential lines being at the same potential, a plurality of dielectric isolation areas extending in the second direction, each of the isolation areas being positioned on the side of each bit line opposite to one of the constant-potential lines, the gate oxide layer extending between adjacent ones of the isolation areas, plural conductive areas extending in the second direction, each of said conductive areas covering one of said isolation areas, plural dielectric layers extending in the second direction, each of the plural dielectric layers extending over one of the conductive areas and the floating gates of plural transistors of the second group, said conductive areas effectively forming electrodes for first, second and third capacitors respectively including as dielectrics the gate oxide layer, one of the dielectric isolation areas and the plural dielectric layers.

Claim 12

A memory having multiple memory points comprising: multiple floating gate MOS transistors arranged on a substrate to correlate with the respective memory points, each of the transistors including a control gate, a floating gate, a source, a drain region of a first conductivity type, a gate oxide layer between the floating gate and the substrate, and a channel in the substrate between the source and drain controlled by voltage applied to the control gate through the gate oxide layer and the floating gate, plural work lines extending in a first direction, each of the word lines interconnecting the transistor control gates of a first group of transistors, plural bit lines extending in a second direction, the first and second directions differing from each other by 90°, each of the bit lines interconnecting the transistor drains of a second group of transistors, the drain region of each transistor in the second group extending in the second direction to form one of the bit lines, said word lines addressing a selected transistor row and said bit lines transmitting a signal indicative of a logic state of the transistors; plural constant-potential lines extending in the second direction, each of the constant potential lines interconnecting the sources of one group of transistors, each of the constant-potential lines including a diffusion of the first conductivity type and being positioned between a pair of adjacent bit lines, all of the constant-potential lines being at the same potential, a plurality of dielectric isolation areas extending in the second direction, each of the isolation areas being positioned on the side of each bit line opposite to one of the constant-potential lines, the gate oxide layer extending between adjacent ones of the isolation areas, plural conductive areas extending in the second direction, each of said conductive areas covering one of said isolation areas, plural dielectric layers extending in the second direction, each of the plural dielectric layers extending over one of the conductive areas and the floating gates of plural transistors of the second group, said conductive areas effectively forming electrodes for first, second and third capacitors respectively including as dielectrics the gate oxide layer, one of the dielectric isolation areas and the plural dielectric layers.

Claim 13

The memory of claim 10 wherein the conductive areas and floating gates are formed of the same material.

Claim 14

The memory of claim 11 wherein said conductive area (E) is formed during the same manufacturing step as the floating gates of said transistors.

Claim 15

The memory of claim 11 wherein each of said conductive areas floats with respect to said word lines, bit lines and substrate.

Claim 16

A memory having multiple memory points comprising: multiple floating gate MOS transistors arranged on a substrate to correlate with the respective memory points, each of the transistors including a control gate, a floating gate, a source, and a drain region of a first conductivity type, plural word lines, each of the word lines interconnecting the transistor control gates of a first group of transistors, plural bit lines, each of the bit lines interconnecting the transistor drains of a second group of transistors, the drain region of each transistor in the second group forming one of the bit lines, said word lines addressing selected transistors in the first group and said bit lines transmitting a signal indicative of a logic state of the transistors; plural constant-potential lines, each of the constant potential lines interconnecting the sources of one group of transistors, each of the constant-potential lines including a diffusion of the first conductivity type and being positioned between a pair of adjacent bit lines, all of the constant-potential lines being at the same potential, a plurality of dielectric isolation areas, each of the isolation areas being positioned on the side of each bit line opposite to one of the constant-potential lines, and plural floating conductive areas, each of said conductive areas covering one of said isolation areas.

Claim 17

A memory having multiple memory points comprising: multiple floating gate MOS transistors arranged on a substrate to correlate with the respective memory points, each of the transistors including a control gate, a floating gate, a source, and a drain region of a first conductivity type, plural word lines, each of the word lines interconnecting the transistor control gates of a first group of transistors, plural bit lines, each of the bit lines interconnecting the transistor drains of a second group of transistors, the drain region of each transistor in the second group forming one of the bit lines, said word lines addressing selected transistors in the first group and said bit lines transmitting a signal indicative of a logic state of the transistors; plural constant-potential lines, each of the constant potential lines interconnecting the sources of one group of transistors, each of the constant-potential lines including a diffusion of the first conductivity type and being positioned between a pair of adjacent bit lines, all of the constant-potential lines being at the same potential, a plurality of dielectric isolation areas, each of the isolation areas being positioned on the side of each bit line opposite to one of the constant-potential lines, and plural floating conductive areas, each of said conductive areas covering one of said isolation areas.

Claim 18

The memory of claim 14 wherein the conductive areas and floating gates are formed of the same material.

Claim 19

The memory of claim 14 wherein each transistor includes: a silicon dioxide layer having a thickness less than 20 nm separating the channel from the floating gate, and wherein the region corresponding to the sources is formed of a highly doped section arranged in a pocket having the same conductivity type and a low doping level, whereby electrons may tunnel through the silicon dioxide layer from the floating gates to the highly doped source region in response to a selected voltage being applied to the source, whereby the memory is electrically erasable.