Erasable read-only semiconductor memory device

Claim 2

A semiconductor memory device comprising: a plurality of memory transistors arranged in a matrix, each said memory transistor having a first conduction electrode, a second conduction electrode and a first control electrode to store information and change a threshold voltage for controlling conduction between said first and second conduction electrodes based on stored information, a plurality of first voltage applying means for applying a first voltage to the respective control electrodes of said plurality of memory transistors, first connection lines connected to the first conduction electrodes of said plurality of memory transistors, and second connection lines continuously maintained at a first predetermined constant voltage and interconnection means for interconnecting continuously each one of said second conduction electrodes of said plurality of memory transistors and said second connection lines, said interconnection means including means for establishing substantially the same value of connection resistance between each one of said second conduction electrodes and said second connection lines.

Claim 3

A semiconductor memory device in accordance with claim 1, wherein said memory transistors are arranged in a plurality of rows and a plurality of columns; said plurality of first voltage applying means are provided corresponding to each row of said plurality of memory transistors; and said first connection lines are provided corresponding to each column of said plurality of memory transistors, a second predetermined voltage being applied to said first connection lines.

Claim 4

A semiconductor memory device in accordance with claim 2, wherein each of said plurality of second connection lines is provided for predetermined columns of said plurality of memory transistors.

Claim 5

A semiconductor memory device in accordance with claim 1, wherein each said memory transistor includes a second control electrode capable of storing electric charge and said second control electrode changes said threshold voltage dependent on whether or not the electric charge is stored.

Claim 6

A semiconductor memory device in accordance with claim 4, wherein said second control electrode includes a floating gate.

Claim 7

A semiconductor memory device in accordance with claim 5, wherein said semiconductor memory device includes an EPROM.

Claim 8

A semiconductor memory device in accordance with claim 4, wherein said plurality of memory transistors are arranged in a plurality of columns and rows in a substrate, each of said second connection lines is formed for one column of said memory transistors, to extend parallel to and along a side thereof on the substrate, and the second control electrode of each said memory transistor is formed to extend to positions between a main surface of said semiconductor substrate and the respective second connection line on both sides of said memory transistor.

Claim 9

A semiconductor memory device in accordance with claim 4, wherein said plurality of memory transistors are arranged in a plurality of columns and rows in a substrate, each of said second connection lines is formed for two columns of said memory transistors, to extend parallel to and along a side of a respective column on the substrate, and the second control electrode of each said memory transistor is formed to extend to positions between a main surface of said semiconductor substrate and the respective second connection line on one side of said memory transistor.

Claim 10

A semiconductor memory device, comprising: a plurality of memory transistors arranged in a matrix of rows and columns, each said memory transistor having a drain electrode, a source electrode and a first control electrode for controlling conduction between said drain and source electrodes based on a threshold voltage representing stored information; a plurality of bit lines for applying a bit line voltage to the drain electrodes of said plurality of memory transistors; ground lines continuously maintained at a predetermined constant voltage; and interconnection means for interconnecting each one of said source electrodes of said plurality of memory transistors and said ground lines, said interconnection means including means for establishing substantially the same value of connection resistance between each one of said source electrodes and said ground lines.

Claim 11

A semiconductor memory device, comprising: a plurality of memory transistors arranged in a matrix of rows and columns, each said memory transistor having a drain electrode, a source electrode and a first control electrode for controlling conduction between said drain and source electrodes based on a threshold voltage representing stored information; a plurality of bit lines for applying a bit line voltage to the drain electrodes of said plurality of memory transistors; ground lines continuously maintained at a predetermined constant voltage; and interconnection means for interconnecting each one of said source electrodes of said plurality of memory transistors and said ground lines, said interconnection means including means for establishing substantially the same value of connection resistance between each one of said source electrodes and said ground lines.

Claim 12

A semiconductor memory device in accordance with claim 9, wherein each said ground line is provided for one column of said memory transistors.

Claim 13

A semiconductor memory device in accordance with claim 9, wherein each said ground line is provided for two columns of said memory transistors.

Claim 14

A semiconductor memory device in accordance with claim 9, wherein each said memory transistor includes a second control electrode capable of storing electric charge and said second control electrode changes said threshold voltage dependent on whether or not the electric charge is stored.

Claim 15

A semiconductor memory device in accordance with claim 12, further comprising: first selection means for selecting an arbitrary one of a plurality of word lines corresponding to said rows, first voltage applying means for applying a first predetermined voltage to the word line selected by said first selection means, second selection means for selecting an arbitrary one of said plurality of bit lines, second voltage applying means for applying said bit line voltage to the bit line selected by said second selection means, and detection means provided for each of said plurality of bit lines, for detecting presence or absence of electric current in the bit line selected by said second selection means.

Claim 16

A semiconductor memory device in accordance with claim 12, further comprising a semiconductor substrate having a main surface, wherein said drain and source electrodes of said memory transistor are formed on a main surface of said semiconductor substrate, said first control electrode is formed in an upper portion of a channel region of said semiconductor substrate between said drain and source electrodes, and said second control electrode is formed between said semiconductor substrate and said first control electrode, said ground lines are provided in the column direction adjacent to the respective columns of said plurality of memory cells and each said ground line is connected to the second conduction electrode of the memory cell of the column adjacent thereto through an impurity region formed on the main surface of said semiconductor substrate, and the second control electrode of each said memory transistor is formed to extend to a position corresponding to the ground line adjacent to said memory transistor.

Claim 17

A semiconductor memory device in accordance with claim 14, wherein the main surface of said semiconductor substrate together with said first and second conduction electrodes is covered with an interlayer insulating film.

Claim 18

A semiconductor memory device in accordance with claim 15, wherein each said ground line is formed on said interlayer insulating film and is connected to said impurity region through a contact hole provided in said interlayer insulating film.

Claim 19

A semiconductor memory device in accordance with claim 16, wherein each said ground line is formed for one column of said memory transistors and the second control electrode of each said memory transistor is formed to extend to positions between the main surface of said semiconductor substrate and the respective ground lines on both sides of said memory transistor.

Claim 20

A semiconductor memory device in accordance with claim 16, wherein each said ground line is formed for two columns of said memory transistors and the second control electrode of each said memory transistor is formed to extend to a position between the main surface of said semiconductor substrate and the ground line on one side of said memory transistor.

Claim 21

A semiconductor memory device in accordance with claim 14, wherein a transistor region including the drain and source electrodes of the memory transistor arranged in the corresponding column as well as the channel region of said semiconductor substrate sandwiched between said first and second conduction electrodes is isolated from a transistor region of the memory transistor arranged in another column adjacent thereto by means of an isolation oxide film formed on the main surface of said semiconductor substrate.

Claim 22

A semiconductor memory device in accordance with claim 19, wherein an area of said second control electrode opposed to said channel region is smaller than that of said first control electrode opposed to said second control electrode, and first and second gate oxide films are formed between said channel region and said second control electrode and between said second control electrode and said first control electrode, respectively.

Claim 23

A semiconductor memory device in accordance with claim 19, wherein said second control electrode includes a floating gate.

Claim 24

A semiconductor memory device in accordance with claim 21, wherein said semiconductor memory device includes an EPROM.

Claim 25

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a plurality of memory transistors arranged in a matrix of rows and columns each memory transistor including: first and second conduction electrodes formed on the main surface of said semiconductor substrate, a first control electrode formed above the main surface of said semiconductor substrate, a first control electrode formed above the main surface of said semiconductor substrate, for controlling conduction between said first and second conduction electrodes based on a voltage applied thereto and a threshold voltage, a second control electrode formed between said semiconductor substrate and said first control electrode and being capable of storing electric charge and changing said threshold voltage dependent on presence or absence of the stored electric charge therein, and ground lines continuously maintained at a first predetermined constant voltage and provided in the column direction adjacent the respective columns of said plurality of memory transistors, and interconnection means for interconnecting each one of said second conduction electrodes of said plurality of memory transistors and said ground lines, said interconnection means including means for establishing substantially the same value of connection resistance between each one of said second conduction electrodes and said ground lines, the second control electrode of each said memory transistor being formed to extend to a position corresponding to the ground line adjacent to said memory transistor.

Claim 26

A semiconductor memory device comprising: a semiconductor substrate having a main surface; a plurality of memory transistors arranged in a matrix of rows and columns each memory transistor including: first and second conduction electrodes formed on the main surface of said semiconductor substrate, a first control electrode formed above the main surface of said semiconductor substrate, a first control electrode formed above the main surface of said semiconductor substrate, for controlling conduction between said first and second conduction electrodes based on a voltage applied thereto and a threshold voltage, a second control electrode formed between said semiconductor substrate and said first control electrode and being capable of storing electric charge and changing said threshold voltage dependent on presence or absence of the stored electric charge therein, and ground lines continuously maintained at a first predetermined constant voltage and provided in the column direction adjacent the respective columns of said plurality of memory transistors, and interconnection means for interconnecting each one of said second conduction electrodes of said plurality of memory transistors and said ground lines, said interconnection means including means for establishing substantially the same value of connection resistance between each one of said second conduction electrodes and said ground lines, the second control electrode of each said memory transistor being formed to extend to a position corresponding to the ground line adjacent to said memory transistor.

Claim 27

A semiconductor memory device in accordance with claim 23, wherein the main surface of said semiconductor substrate together with said first and second conduction electrodes is covered with an interlayer insulating film.

Claim 28

A semiconductor memory device in accordance with claim 24, wherein each said ground line is formed on said interlayer insulating film and is connected to said impurity region through a contact hole provided in said interlayer insulating film.

Claim 29

A semiconductor memory device in accordance with claim 25, wherein each said ground line is formed for one column of said memory transistors and the second control electrode of each said memory transistor is formed to extend to positions between the main surface of said semiconductor substrate and the respective ground lines on both sides of said memory transistor.

Claim 30

A semiconductor memory device in accordance with claim 25, wherein each said ground line is formed for two columns of said memory transistors and the second control electrode of each said memory transistor is formed to extend to a position between the ground line on one side of said memory transistor and the main surface of said semiconductor substrate.

Claim 31

A semiconductor memory device in accordance with claim 23, wherein a transistor region including the first and second conduction electrodes of the memory transistor arranged in the corresponding column as well as the channel region of said semiconductor substrate sandwiched between said first and second conduction electrodes is isolated from a transistor region of the memory transistor arranged in another column adjacent thereto by means of an isolation oxide film formed on the main surface of said semiconductor substrate.

Claim 32

A semiconductor memory device in accordance with claim 28, wherein an area of said second control electrode opposed to said channel region is smaller than that of said first control electrode opposed to said second control electrode, and first and second gate oxide films are formed between said channel region and said second control electrode and between said second control electrode and said first control electrode, respectively.

Claim 33

A semiconductor memory device in accordance with claim 29, wherein the first conduction electrode, the channel region and the second conduction electrode of each said memory transistor are formed in the column direction and said first control electrode is connected with the first control electrode of the memory transistor of the same row and of the column adjacent thereto.

Claim 34

A semiconductor memory device in accordance with claim 30, wherein said second control electrode includes a floating gate.

Claim 35

A semiconductor memory device in accordance with claim 31, wherein said semiconductor memory device includes an EPROM.