Nonvolatile semiconductor memory device

Claim 2

A nonvolatile semiconductor memory device comprising: at least one memory cell consisting of an MOS transistor with a floating gate; at least one word line coupled to the gate of the MOS transistor of said at least one memory cell to selectively transmit an access signal to said at least one memory cell; at least one data line coupled to the drain of the MOS transistor of said at least one memory cell to transmit data to be transferred to and from said memory cell; and potential level control means, coupled to the source of the MOS transistor of said at least one memory cell, for maintaining the source potential of said MOS transistor substantially at a given level higher than the substrate potential of said MOS transistor.

Claim 3

A nonvolatile semiconductor memory device according to claim 1, wherein said potential level control means is formed of first resistance means.

Claim 4

A nonvolatile semiconductor memory device according to claim 2, wherein said potential level control means includes a series combination of a second resistance means and switching means coupled in parallel with said first resistance means.

Claim 5

A nonvolatile semiconductor memory device according to claim 1, wherein said potential level control means includes: a first control signal generation means having an input terminal coupled to the source of the MOS transistor of said memory cell, for producing a control signal when the voltage level of an input signal reaches a given value; and a first MOS transistor having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof the control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said control signal.

Claim 6

A nonvolatile semiconductor memory device according to claim 4, wherein said first control signal generation means includes: a voltage generation means to produce a voltage at the same level as a potential level that said data line will attain when energized; a second MOS transistor having a drain coupled to said voltage generation means and formed in the same configuration with the MOS transistor of said memory cell; and means for comparing the source potentials of said second MOS transistor and the MOS transistor of said memory cell and producing a control signal to change the conduction resistance of said first MOS transistor.

Claim 7

A nonvolatile semiconductor memory device according to claim 4, wherein said first control signal generation means includes a comparator circuit for comparing the source voltage of the MOS transistor for said memory cell with a first reference voltage.

Claim 8

A nonvolatile semiconductor memory device according to claim 4, wherein said first control device generation means includes an inverter circuit.

Claim 9

A nonvolatile semiconductor memory device comprising: a plurality of memory cells each consisting of an MOS transistory with a floating gate and arranged in the form of a matrix; a plurality of word lines each coupled to the gates of the MOS transistors of memory cells arranged on the same row to transmit an access signal to said memory cells; a plurality of data lines each coupled to the drains of the MOS transistors of memory cells arranged on the same column to transmit data to be transferred to and from said memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors substantially at a given level higher than the substrate potential of said MOS transistors.

Claim 10

A nonvolatile semiconductor memory device comprising: a plurality of memory cells each consisting of an MOS transistory with a floating gate and arranged in the form of a matrix; a plurality of word lines each coupled to the gates of the MOS transistors of memory cells arranged on the same row to transmit an access signal to said memory cells; a plurality of data lines each coupled to the drains of the MOS transistors of memory cells arranged on the same column to transmit data to be transferred to and from said memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors substantially at a given level higher than the substrate potential of said MOS transistors.

Claim 11

A nonvolatile semiconductor memory device according to claim 8, wherein said potential level control means is formed of first resistance means.

Claim 12

A nonvolatile semiconductor memory device according to claim 9, wherein said potential level control means including a series combination of a second resistance means and switching means coupled in parallel with said first resistance means.

Claim 13

A nonvolatile semiconductor memory device according to claim 8, wherein said potential level control means includes: a first control signal generation means, having an input terminal coupled to the source of the MOS transistor of said memory cell, for producing a control signal when the voltage level of an input signal reaches a given value; and a first MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof the control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said control signal.

Claim 14

A nonvolatile semiconductor memory device according to claim 11, wherein said first control signal generation means includes a comparator circuit for comparing the source voltage of the MOS transistors for said memory cells with a first reference voltage.

Claim 15

A nonvolatile semiconductor memory device according to claim 11, wherein said first control signal generation means includes an inverter circuit.

Claim 16

A nonvolatile semiconductor memory device according to claim 11, wherein said first control signal generation means includes: a voltage generation means to produce a voltage at the same level as a potential level that said data line will attain when energized; a second MOS transistor having a drain coupled to said voltage generation means and formed in the same configuration with the MOS transistors of said memory cells; and means for comparing the source potentials of said second MOS transistors and the MOS transistor of said memory cells and producing a control signal to change the conduction resistance of said first MOS transistor.

Claim 17

A nonvolatile semiconductor memory device comprising: at least one word line; a plurality of memory cells each consisting of an MOS transistor having a floating gate and a control gate coupled to said at least one word line; a plurality of data lines coupled selectively to the drains of the MOS transistors of said plurality of memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors substantially at a given level higher than the substrate potential of said MOS transistors.

Claim 18

A nonvolatile semiconductor memory device comprising: at least one word line; a plurality of memory cells each consisting of an MOS transistor having a floating gate and a control gate coupled to said at least one word line; a plurality of data lines coupled selectively to the drains of the MOS transistors of said plurality of memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors substantially at a given level higher than the substrate potential of said MOS transistors.

Claim 19

A nonvolatile semiconductor memory device according to claim 15, wherein said potential level control means is formed of first resistance means.

Claim 20

A nonvolatile semiconductor memory device according to claim 16, wherein said potential level control means includes a series combination of a second resistance means and switching means coupled in parallel with said first resistance means.

Claim 21

A nonvolative semiconductor memory device according to claim 15, wherein said potential level control means includes: a first control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells, for producing a control signal when the voltage level of an input signal reaches a given value; and a first MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gate thereof the control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said control signal.

Claim 22

A nonvolatile semiconductor memory device according to claim 18, wherein said first control signal generation means includes a comparator circuit for comparing the source voltage of the MOS transistors for said memory cells with a first reference voltage.

Claim 23

A nonvolatile semiconductor memory device according to claim 18, wherein said first control signal generation means includes an inverter circuit.

Claim 24

A nonvolatile semiconductor memory device according to claim 18, wherein said first control signal generation means includes: a voltage generation means to produce a voltage at the same level as a potential level that said data line will attain when energized; a second MOS transistor having a drain coupled to said voltage generation means and formed in the same configuration with the MOS transistors of said memory cells; and means for comparing the source potentials of said second MOS transistor and the MOS transistors of said memory cells and producing a control signal to change the conduction resistance of said first MOS transistor.

Claim 25

A nonvolatile semiconductor memory device comprising: at least one memory cell including an MOS transistor with a floating gate; at least one word line coupled to the gate of the MOS transistor of said at least one memory cell to selectively transmit an access signal to said at least one memory cell; at least one data line coupled to the drain of the MOS transistor of said at least one memory cell to transmit data to be transferred to and from said memory cell; and potential level control means coupled to the source of the MOS transistor of said at least one memory cell, for maintaining the source potential of said MOS transistor at a level higher than the potential of the substrate of said MOS transistor, said potential level control means including: (i) a first control signal generation means, having an input terminal coupled to the source of the MOS transistor of said memory cell, for producing a first control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, (ii) a first MOS transistor with a gate and having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof said first control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said first control signal, (iii) a second control signal generation means, having an input terminal coupled to the source of the MOS transistor of said memory cell, for producing a second control signal when the voltage level of an input signal to said second control signal generation means and reaches a given value, (iv) a second MOS transistor with a gate and having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof said second control signal from said second control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said second control signal.

Claim 26

A nonvolatile semiconductor memory device comprising: at least one memory cell including an MOS transistor with a floating gate; at least one word line coupled to the gate of the MOS transistor of said at least one memory cell to selectively transmit an access signal to said at least one memory cell; at least one data line coupled to the drain of the MOS transistor of said at least one memory cell to transmit data to be transferred to and from said memory cell; and potential level control means coupled to the source of the MOS transistor of said at least one memory cell, for maintaining the source potential of said MOS transistor at a level higher than the potential of the substrate of said MOS transistor, said potential level control means including: (i) a first control signal generation means, having an input terminal coupled to the source of the MOS transistor of said memory cell, for producing a first control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, (ii) a first MOS transistor with a gate and having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof said first control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said first control signal, (iii) a second control signal generation means, having an input terminal coupled to the source of the MOS transistor of said memory cell, for producing a second control signal when the voltage level of an input signal to said second control signal generation means and reaches a given value, (iv) a second MOS transistor with a gate and having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof said second control signal from said second control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said second control signal.

Claim 27

A nonvolatile semiconductor memory device according to claim 22, wherein said first and second control signal generation means include first and second comparator circuits for comparing the source voltage of the MOS transistor of said memory cell with first and second reference voltages, and first and second switching means having current paths coupled respectively to the output terminals of said first and second comparator circuits and energized alternately.

Claim 28

A nonvolatile semiconductor memory device according to claim 22, wherein said first and second control signal generation means include first and second inverter circuits and first and second switching means having current paths coupled respectively to the output terminals of said first and second inverter circuits and energized alternately.

Claim 29

A nonvolatile semiconductor memory device comprising: at least one memory cell including an MOS transistor with a floating gate; at least one word line coupled to the gate of the MOS transistor of said at least one memory cell to selectively transmit an access signal to said at least one memory cell; at least one data line coupled to the drain of the MOS transistor of said at least one memory cell to transmit data to be transferred to and from said memory cell; and potential level control means coupled to the source of the MOS transistor of said at least one memory cell, for maintaining the source potential of said MOS transistor at a level higher than the potential of the substrate of said MOS transistor, said potential level control means including: (i) a first control signal generation means for producing a control signal when the voltage level of an input signal to said first control signal generation means signal reaches a given value, said first control signal generation means including an input terminal coupled to the source of the MOS transistor of said memory cell resistance means with one end coupled to a power supply terminal, and a first MOS transistor coupled between the source of the MOS transistor of said memory cell and the other end of said resistance means, said control signal being produced from a junction between said resistance means and said first MOS transistor when the voltage level of said input signal reaches a given value, and (ii) a second MOS transistor with a gate and having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof the control signal from said first control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said control signal.

Claim 30

A nonvolatile semiconductor memory device comprising: at least one memory cell including an MOS transistor with a floating gate; at least one word line coupled to the gate of the MOS transistor of said at least one memory cell to selectively transmit an access signal to said at least one memory cell; at least one data line coupled to the drain of the MOS transistor of said at least one memory cell to transmit data to be transferred to and from said memory cell; and potential level control means coupled to the source of the MOS transistor of said at least one memory cell, for maintaining the source potential of said MOS transistor at a level higher than the potential of the substrate of said MOS transistor, said potential level control means including: (i) a first control signal generation means for producing a control signal when the voltage level of an input signal to said first control signal generation means signal reaches a given value, said first control signal generation means including an input terminal coupled to the source of the MOS transistor of said memory cell resistance means with one end coupled to a power supply terminal, and a first MOS transistor coupled between the source of the MOS transistor of said memory cell and the other end of said resistance means, said control signal being produced from a junction between said resistance means and said first MOS transistor when the voltage level of said input signal reaches a given value, and (ii) a second MOS transistor with a gate and having a current path coupled to the source of the MOS transistor of said memory cell and receiving at the gate thereof the control signal from said first control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said control signal.

Claim 31

A nonvolatile semiconductor memory device according to claim 25, wherein said first control signal generation means further includes a voltage generation means to produce a voltage at the same level as a potential level that said data line will attain when energized, and a third MOS transistor having a current path coupled between said voltage generation means and the gate of said second MOS transistor and formed in the same configuration as the MOS transistor of said memory cell.

Claim 32

A nonvolatile semiconductor memory device according to claim 25, wherein said second MOS transistor is coupled to the source of the MOS transistor of said memory cell through a resistance-type MOS transistor.

Claim 33

A nonvolatile semiconductor memory device comprising: a plurality of memory cells each including an MOS transistor with a floating gate and arranged in the form of a matrix with rows and columns; a plurality of word lines each coupled to the gates of the MOS transistors of memory cells arranged on the same row to transmit an access signal to said memory cells; a plurality of data lines each coupled to the drains of the MOS transistors of memory cells arranged on the same column to transmit data to be transferred to and from said memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, said potential level control means including: (i) a first control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells, for producing a first control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, (ii) a first MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gate thereof said first control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said first control signal, (iii) a second control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells, for producing a second control signal when the voltage level of an input signal to said second control signal generation means reaches a given value, and (iv) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gate thereof said second control signal from said second control signal generations means so that the conduction state of said second MOS transistor may be controlled in accordance with said second control signal.

Claim 34

A nonvolatile semiconductor memory device comprising: a plurality of memory cells each including an MOS transistor with a floating gate and arranged in the form of a matrix with rows and columns; a plurality of word lines each coupled to the gates of the MOS transistors of memory cells arranged on the same row to transmit an access signal to said memory cells; a plurality of data lines each coupled to the drains of the MOS transistors of memory cells arranged on the same column to transmit data to be transferred to and from said memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, said potential level control means including: (i) a first control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells, for producing a first control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, (ii) a first MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gate thereof said first control signal from said first control signal generation means so that the conduction state of said first MOS transistor may be controlled in accordance with said first control signal, (iii) a second control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells, for producing a second control signal when the voltage level of an input signal to said second control signal generation means reaches a given value, and (iv) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gate thereof said second control signal from said second control signal generations means so that the conduction state of said second MOS transistor may be controlled in accordance with said second control signal.

Claim 35

A nonvolatile semiconductor memory device according to claim 28, wherein said first and second control signal generation means include first and second comparator circuits for comparing the source voltage of the MOS transistors of said memory cells with first and second reference voltages, and first and second switching means having current paths coupled respectively to the output terminals of said first and second comparator circuits and energized alternately.

Claim 36

A nonvolatile semiconductor memory device according to claim 28, wherein said first and second control signal generation means include first and second inverter circuits and first and second switching means having current paths coupled respectively to the output terminals of said first and second inverter circuits and energized alternately.

Claim 37

A nonvolatile semiconductor memory device comprising: a plurality of memory cells each including an MOS transistor with a floating gate and arranged in the form of a matrix having rows and columns; a plurality of word lines each coupled to the gates of the MOS transistors of memory cells arranged on the same row to transmit an access signal to said memory cells; a plurality of data lines each coupled to the drains of the MOS transistors of memory cells arranged on the same column to transmit data to be transferred to and from said memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, said potential level control means including: (i) a first control signal generation means for producing a control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, said first control signal generation means including an input terminal coupled to the source of the MOS transistors of said memory cells, resistance means with one end coupled to a power supply terminal, and a first MOS transistor coupled between the sources of the MOS transistors of said memory cells and the other end of said resistance means, said control signal being produced from a junction between said resistance means and said first MOS transistor when the voltage level of said input signal reaches a given value, and (ii) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof the control signal from said first control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said control signal.

Claim 38

A nonvolatile semiconductor memory device comprising: a plurality of memory cells each including an MOS transistor with a floating gate and arranged in the form of a matrix having rows and columns; a plurality of word lines each coupled to the gates of the MOS transistors of memory cells arranged on the same row to transmit an access signal to said memory cells; a plurality of data lines each coupled to the drains of the MOS transistors of memory cells arranged on the same column to transmit data to be transferred to and from said memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, said potential level control means including: (i) a first control signal generation means for producing a control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, said first control signal generation means including an input terminal coupled to the source of the MOS transistors of said memory cells, resistance means with one end coupled to a power supply terminal, and a first MOS transistor coupled between the sources of the MOS transistors of said memory cells and the other end of said resistance means, said control signal being produced from a junction between said resistance means and said first MOS transistor when the voltage level of said input signal reaches a given value, and (ii) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof the control signal from said first control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said control signal.

Claim 39

A nonvolatile semiconductor memory device according to claim 31, wherein said first control signal generation means further includes a voltage generation means to produce a voltage at the same level as a potential level that said data line will attain when energized, and a third MOS transistor having a current path coupled between said voltage generation means and the gate of said second MOS transistor and formed in the same configuration as the MOS transistor of said memory cell.

Claim 40

A nonvolatile semiconductor memory device according to claim 31, wherein said first MOS transistor is coupled to the source of the MOS transistor of said memory cell through a resistance-type MOS transistor.

Claim 41

A nonvolatile semiconductor memory device comprising: at least one word line; a plurality of memory cells each including an MOS transistor having a floating gate and a control gate coupled to said at least one word line; a plurality of data lines coupled selectively to the drains of the MOS transistors of said plurality of memory cells; and potential level control means coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, and said potential level control means including: (i) a first control signal generation means, having an input terminal coupled to the source of the MOS transistors of said memory cells, for producing a first control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, (ii) a first MOS transistor having a current path coupled to the source of the MOS transistors of said memory cells and receiving at the gates thereof said first control signal from said first control signal generations means so that the conduction state of said first MOS transistor may be controlled in accordance with said first control signal, (iii) a second control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells for producing a second control signal when the voltage level of an input signal to said second control signal generation means reaches a given value, and (iv) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof said second control signal from said second control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said second control signal.

Claim 42

A nonvolatile semiconductor memory device comprising: at least one word line; a plurality of memory cells each including an MOS transistor having a floating gate and a control gate coupled to said at least one word line; a plurality of data lines coupled selectively to the drains of the MOS transistors of said plurality of memory cells; and potential level control means coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, and said potential level control means including: (i) a first control signal generation means, having an input terminal coupled to the source of the MOS transistors of said memory cells, for producing a first control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, (ii) a first MOS transistor having a current path coupled to the source of the MOS transistors of said memory cells and receiving at the gates thereof said first control signal from said first control signal generations means so that the conduction state of said first MOS transistor may be controlled in accordance with said first control signal, (iii) a second control signal generation means, having an input terminal coupled to the sources of the MOS transistors of said memory cells for producing a second control signal when the voltage level of an input signal to said second control signal generation means reaches a given value, and (iv) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof said second control signal from said second control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said second control signal.

Claim 43

A nonvolatile semiconductor memory device according to the claim 34, wherein said first and second control signal generation means include first and second comparator circuits for comparing the source voltage of the MOS transistors of said memory cells with first and second reference voltages, and first and second switching means having current paths coupled respectively to the output terminals of said first and second comparator circuits and energized alternately.

Claim 44

A nonvolatile semiconductor memory device according to claim 34, wherein said first and second control signal generation means includes first and second inverter circuits and first and second switching means having current paths coupled respectively to the output terminals of said first and second inverter circuits and energized alternately.

Claim 45

A nonvolatile semiconductor memory device comprising: at least one word line; a plurality of memory cells each including an MOS transistor having a floating gate and a control gate coupled to said at least one word line; a plurality of data lines coupled selectively to the drains of the MOS transistors of said plurality of memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, said potential level control means including: (i) a first control signal generation means for producing a control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, said first control signal generation means including an input terminal coupled to the source of the MOS transistors of said memory cells, resistance means with one end coupled to a power supply terminal, and a first MOS transistor coupled between the source of the MOS transistors of said memory cells and the other end of said resistance means, said control signal being produced from a junction between said resistance means and said first MOS transistor when the voltage level of said input signal reaches a given value, and (ii) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof the control signal from said first control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said control signal.

Claim 46

A nonvolatile semiconductor memory device comprising: at least one word line; a plurality of memory cells each including an MOS transistor having a floating gate and a control gate coupled to said at least one word line; a plurality of data lines coupled selectively to the drains of the MOS transistors of said plurality of memory cells; and potential level control means, coupled to the sources of the MOS transistors of at least part of said plurality of memory cells, for maintaining the source potential of said MOS transistors at a level higher than the potential of the substrate of said MOS transistors, said potential level control means including: (i) a first control signal generation means for producing a control signal when the voltage level of an input signal to said first control signal generation means reaches a given value, said first control signal generation means including an input terminal coupled to the source of the MOS transistors of said memory cells, resistance means with one end coupled to a power supply terminal, and a first MOS transistor coupled between the source of the MOS transistors of said memory cells and the other end of said resistance means, said control signal being produced from a junction between said resistance means and said first MOS transistor when the voltage level of said input signal reaches a given value, and (ii) a second MOS transistor having a current path coupled to the sources of the MOS transistors of said memory cells and receiving at the gates thereof the control signal from said first control signal generation means so that the conduction state of said second MOS transistor may be controlled in accordance with said control signal.

Claim 47

A nonvolatile semiconductor memory device according to claim 37, wherein said first control signal generation means further includes a voltage generation means to produce a voltage at the same level as a potential level that said data line will attain when energized, and a third MOS transistor having a current path coupled between said voltage generation means and the gate of said second MOS transistor and formed in the same configuration as the MOS transistors of said memory cells.

Claim 48

A nonvolatile semiconductor memory device according to claim 37, wherein said first MOS transistor is coupled to the sources of the MOS transistors of said memory cells through a resistance-type MOS transistor.